The A500 did not have 70 nanosecond memory capable of 14 MHz bus access and therefore the CPU and chipset had to split the 7 MHz bus speed between themselves taking every other clock cycle for each.
I'm sorry but you are talking bollocks. In every Amiga chipset (OCS/ECS/AGA) the Chip RAM memory bus is run at ~3.5 MHz. The CPU can access every other memory cycle at most while the chipset DMA can access all of them (and can block the CPU for long periods).