MiniMig with AGA

[yaqube]

Can the DAC also do sampling in? Of course that would require a Mic input...

No, a DAC connot sample incoming signal. That's the task for an ADC (or a codec which integrates DACs and ADCs).

[yaqube]

Any link that describe the "Replay" hardware in detail?

Only schematics available.

[yaqube]

Am I to understand that this is just 1 DAC, capable of a single audio channel of output?

That was a little bit misleading, actually it's one stereo DAC IC containing two separate DACs, each for left and right channel.

If it is DMA driven then why does the CPU need to do mixing?

Because it supports only one (stereo) channel. To off load the CPU we need more hardware channels. It's really frustrating to see the CPU fully loaded mixing four audio channels with decent rate when the same job can be done by Paula with almost no CPU load. Definitely we need more hardware channels.

This is hardware mixed in FPGA code, correct?

Yep, the four Paula native audio channels and two 16-bit ones are down-mixed in hardware.

[yaqube]

What format does the DAC IC take?  1 word left + 1 word right, repeat.  ?

Exactly, the words the DAC is fed can contain up to 24 meaningful bits. For further details please have a look at the DAC's datasheet.

That is the DAC IC reads 1 DMA stream of data to produce 1 stereo ouput?

Not exactly, the DAC is fed with the data stream from the I2S controller (located in the FPGA). This stream contains down-mixed data from Paula's  audio channels and from the AHI stereo channel (the AHI sound is provided by the extra DMA controller).

While Paula reads 2 distinct DMA streams of data to produce 1 stereo output.

Actually Paula reads 4 mono channels and down-mix them to form two channels for stereo output (two mono channels go to the left and two to the right). This stereo output is further down-mixed with stereo output from AHI sound module and is sent to the DAC IC.

[yaqube]

Since the spartan 3e wont give use speeds beyond 20Mhz

Actually there is a hope it will work at 28 MHz. I have it currently running at that speed and with a very small cache (for code only) of 16 bytes it outperforms an 030@25MHz.



I'm working on the implementation of a more sophisticated cache subsystem. I expect the performance to be improved a little bit.

wouldn't it make sense that someone worked in porting the DCTV hardware (that would allow high color resolutions without requiring lots of memory or bandwidth)

Sometime ago I wrote a software decoder for DCTV encoded images just to find out how it worked. Initially I wanted to implement this decoder into the Minimig AGA but I think it's not worth the hassle. Let's better spend that time on a real RTG frame buffer implementation.

and hopefully someone would write a RTG driver for it.

I can bet nobody will.

[yaqube]

Results for 28 MHz clock and 256-byte instruction cache. Maybe the speed gain is not impressive but I have yet another option to try.

[yaqube]

I'm sorry if this has been answered already, but what is missing from m68k/32 for it to be 68020 compatible?

The main source of incompatibility is the lack of support for bitfield instructions and word/long word access at odd addresses.

[yaqube]

Just a small update. The CPU core is still clocked at 28 MHz but this time with two separate 256-byte instruction and data caches.

[yaqube]

Is there any performance optimimum like for the instruction cache where 16-bytes gives a significant boost, but 256-bytes only gives 7% more performance increase.

It heavily depends on application. The 16-byte cache gives significant boost because it's one line of 16 bytes and actually acts as a prefetch buffer. Data from memory are always transferred as a burst of 4 32-bit words (which gives 16 bytes). After initial transfer latency the successive words can be accessed at no delay.

Maybe prefetch could be useful ? , because every RAM-fetch from memory require a significant setup time. So reading a few extra bytes in advance might be benefitial?

It's been already done. When I added the data cache I also implemented an extra instruction cache prefetch. The speed gain is 18%.

How is compatability?

The work is far from complete but there exist some programs which work.

[yaqube]

Is there a gain in speed for hdf read/write ?

The hdf read speed has increased by 5% to 2000 KB/s.

[yaqube]

Clock for clock, that makes your implementation about twice as fast as a real 68020/68030

Actually it's not mine, the whole CPU core was designed by Tobias. I only added caches to allow it to work at full speed. Despite it's not complete yet the job done by Tobias is excellent.

[yaqube]

I want to know about the fpgaarcade´s power consumption, how much is it?

The current consumption of the Replay board running the latest Minimig AGA core with a mouse and keyboard connected is 600 mA (max). It seems 1 A is more than enough for the base board.

[yaqube]

Finally I have had some time to make tests with my new Replay expansion board. I was very curious how fast the 060 rev. 6 can run. It was able to run very stable from 3.3V with a very small heat sink and fan at over 100 MHz.