In general - yes, it can. It depends on the load the DMA operation puts onto the bus(ses).
Not necessarily. If there's a bootleneck that gets saturated by DMA, other stuff gets slowed to a halt. A standard PCI bus saturated by gigabit ethernet can do nothing else, e.g. serve I/O requests for HDD. Modern systems increasingly avoid bootlenecks, PCI Express is no physical bus any more for instance. On older Pentium III age systems you could easily saturate the memory interface with fast I/O for SCSI or Ethernet, but a modern system can have dual channel 1333 MHz RAM (or faster), a theoretical throughput of 16 bytes x 1333 MHz ~= 20 GB/s - extremely heavy duty hardware aside, there's nothing on the planet able to saturate that interface. If the PCIe subsystem is properly crossbar-switched you can't saturate that either.
So, any DMA operation just competes for memory time slots. If there's plenty, the CPU will have to yield the bus only for extremely short times - depending on what's running that may not even be noticeable. OTOH, today's CPUs are so fast that they're practically waiting for the slow RAM all the time... 
Anyway, DMA is much more efficient since the data has to go through the bus only once. For PIO, the CPU needs to read the data from the device and write it to memory, the memory load is doubled. Additionally, status registers need to be polled, increasing the load even more. Furthermore, the CPU (or one core/thread) is busy handling the I/O.
See the cache as a separate bus that's running independently.
Yes! That's the plan. Chip DMA competes for chip bus time alone. The CPU competes for fast bus time with the (mostly Zorro) DMA devices present. For chip RAM access it needs to compete for both(!) simultaneously.
No.
Sounds like a crossbar switch.
you sir, are completely correct.
