minimig 4000

[HenryCase]

Akiko wrote:
Will you be financing this ambitious creation?

This project isn't ambitious enough for the amount of work necessary. I do agree that if A6000 wants to get this started he should put up some of the funds though.

A6000, the project you want isn't best served with a Minimig-based solution, you'd be much better off with Clone-A.

http://www.amigahistory.co.uk/clone-a.html

Only mentions OCS in that link, but AFAIK work on AGA is well under way.

Way I see it is Clone-A and Minimig complement each other. Clone-A is about perfect reproduction of the past, whilst Minimig (+AROS) gives an opportunity to take complete control of the future.

[HenryCase]

downix wrote:
How about we get an A2000 replacement going first, then let's work on the next step?

An A2000 clone Minimig (with the expansion options) is what I see as the next major step forward for the Minimig. I'm working on something now that needs A2000 compatibility, so of course I'd say that!

A6000, the negativity is arising because you need to think practically about this project idea. I appreciate you've said that you're not able to help with the technical aspects of implementing your design, so why not do something about that? I've started to learn Verilog so I can help, using this tutorial, I recommend you do the same:
http://www.asic-world.com/verilog/veritut.html

[HenryCase]

amigakit said:
Work on Clone-A is still ongoing and progressing - but this project will hopefully make commercial Amiga hardware more viable.

Amigakit, I'm glad to hear progress is still being made on the Clone-A, haven't had much news around for a few months, have you heard anything from Jens or Oliver recently?

amigadave said:
Well said!

Thanks amigadave! :-D

downix said:
If you want the CPU fast-slot I have the design 90% done with my neo-A500 sidecar slot design.

Thanks downix. As it happens it is the A2000 CPU slot that I need for my project. Is this really very similar to the A500 sidecar slot?

I don't want to say too much about my project at the moment, because it might not come to anything, still very early days. When I've got some concrete signs of progress I'll be posting on a.org for assistance.

[HenryCase]

downix wrote:

HenryCase wrote:

downix said:
If you want the CPU fast-slot I have the design 90% done with my neo-A500 sidecar slot design.

Thanks downix. As it happens it is the A2000 CPU slot that I need for my project. Is this really very similar to the A500 sidecar slot?

I don't want to say too much about my project at the moment, because it might not come to anything, still very early days. When I've got some concrete signs of progress I'll be posting on a.org for assistance.

yes, only 2 pins different.  So, close enough that it can easily be adapted.

That's great news downix. Fingers crossed your Minimig improvement project goes smoothly.

[HenryCase]

amigadave wrote:
Hmmm, thinking out loud.  Since the Coldfire had that hardware translator removed and since many have wanted to develop a Coldfire accel for the Amiga because of the Coldfire's low cost and availability, as well as its increased speed, maybe we could get Dennis to sit down for another year and develop the missing 68060 part of the Coldfire in an FPGA and we would end up with a real A3000/A4000 Coldfire accelerator that works and runs at 3 to 10 times faster than our old Phase5 060 boards?

If it were that simple, I guess someone would have done it already. :-?

amigadave, couple of things:
1. Dennis has already done enough hard work for us on this project already. Anything else we get from him is a huge bonus IMO.
2. TobiFlex has already implemented a Minimig+68000 on FPGA. This solution isn't open source yet but hopefully it will be soon. An A500 wouldn't use the extra instructions of an 68060, right?
3. As we already have a 68000 on FPGA, we could easily overclock it an get some of the speed improvements you are looking for.

There would be two things that limited overclocking; the maximum speed of the FPGA and the clock speed of the Amiga (which we cannot change AFAIK). Some useful overclocking info on this website (http://members.iinet.net.au/~davem2/amiga.html):
"Firstly is the computer being modified of "synchronous" or "asynchonous" design? Synchronous is where the CPU is clocked at a speed which is a direct multiple of the main clock which runs the entire computer."

If the main A500 clock runs at approximately 7.14MHz, we should be able to overclock the 'processor' part of the FPGA to high speeds for an Amiga CPU if we stick to multiples of this base value (121.38MHz, 164.22MHz, etc...). Anyone know what the maximum clock speed for a Spartan-3 FPGA is?

[HenryCase]

Alexh, thank you for that info.

alexh said:
"If not, a standard 680x0 program will use the improved architecture, parallel execution units, Instruction and data cache, branch prediction etc."

I'd like to break down that statement so I have a better chance of understanding it:

"Improved architecture". Are you referring to refinements to existing operations (i.e. streamlined instruction architecture) or the addition of new facilities (i.e. more data bandwidth)?
"Parallel execution units" How does the 68060 do this? I didn't think the 68K series CPUs were parallel processors in the modern sense. Did it have multiple ALUs/FPUs, more registers, bigger instruction pipelines?
"Instruction and data cache" Are you referring to the increased space for more complex operations (complex in the sense that the 68060 could do larger calculations in a smaller number of cycles)?
"Branch prediction" You've lost me there. How does this work?

alexh said:
"It doesnt work like that."

Care to explain why we wouldn't be able to 'overclock' the 68000 in the way I described? Surely all timing is set on the FPGA. What would 'overclocking' the 68000 code break in the Minimig?

alexh said:
"FPGA's dont really have a "maximum clock speed". Their maximum speed is determined partly by type/generation of FPGA it is and mainly by the logic that is programmed into them.

While the FPGA might be rated to 300MHz, when programmed it wont do a fraction of that speed!

Maybe low 10's of MHz with a well written design. Certainly not 100's."

I have heard this before, in my enthusiasm for the overclocking idea I forgot that the maximum speed of FPGAs is determined by the complexity of their design as well as FPGA type. My question is, what does that 300MHz rating even mean, how is it calculated?

Thanks in advance for your help.

[HenryCase]

amigadave wrote:
@HenryCase,

I was not thinking of just speeding up the MiniMig a little so games would run faster, or at the correct speed.  I am thinking of future projects where people will be working on advanced Amiga compatible designs by using the work Dennis has started and forwarding it up to and beyond anything we currently have in hardware on Classic Amigas.  This could include using 68060 CPUs, but it would be better if a Coldfire solution could be designed, as it is faster, cheaper and more available, and it is an extension of the 68000 series CPU.  Another group will probably go in the direction of PPC CPUs to obtain compatibility with AmigaOS4.x and yet another group will move toward integration with x86 architectures to use AROS and take advantage of all the cheap hardware.

I think one of the next steps will be to have ECS and AGA recreation in hardware and then go beyond to what AAA would have been.

amigadave, you made a very good point by illustrating the different ways the Amiga community will want to take the Minimig. As I wasn't considering all the possibilities when I made my comments about your previous post I didn't give your ideas fair consideration and for this I apologise.

I don't have a problem with any ideas for Minimig expansions, the more options we have the better the project as a whole becomes. However, I am concerned with making sure the Minimig is improved as fast as possible to make it a viable source of new Amiga hardware rather than making it a bit of a curio. For the amount of work necessary to make these big hardware improvements I tend to see the PPC route as the one with the most immediate potential. When the hardware is sufficiently powerful then we have more time to explore other uses of the tech. IMHO.

AeroMan wrote:
I think if AGA compatibility is the target, we should have that in mind when doing any board. The hardware should be capable of supporting it, and we can grow the software slowly from OCS to ECS and then AGA without doing new boards. This keeps costs acceptable for us hobbists.

Aeroman, this is very important, and it's something that hasn't been discussed much. The key to doing this is expandibility, which is the one major weakness with the v1.1 PCB. Let's say an AGA solution was made. It seems very likely that AGA wouldn't fit on the current design, so those people who want it have no choice but to upgrade to a newer PCB revision. If we had something like the CPU Fast Slot then we could design an upgrade board for the existing design, with an FPGA providing the extra processing capacity. People who hadn't bought a Minimig before this time could just buy a newer version of the PCB with the expanded capabilities built in.

I don't know if Minimig v1.1 had enough I/O pins on the FPGA to handle an expansion port, but if TobiFlex does release his code then we'll have plenty more I/O pins to play with. Downix, how many pins does your A500-like expansion port need?

If an expansion port is included in v1.2 a greater number of early adopters have more versatile hardware sooner, which in turn will speed up development. Any thoughts?

[HenryCase]

AJCopland wrote:
I think there's more to having AGA support than just changing the Verilog. It'll need the data and probably address buses upgrading to 32bit as well as running at a higher clock speed. Then to actually support software which expects AGA you'll probably need at least an '020 processor.

AJCopland, I agree about the 68020 requirement for AGA Amigas, but would argue that this is even more reason to have two FPGAs. I'd certainly prefer 2x FPGAs than 1x FPGA and 1x 68020, simply because this is a more flexible design and frees us from components that may not be supported forever.

Also a CPU fast slot isn't going to make a v1.2 any better at supporting AGA as it'll still be connecting to the same FPGA via the same 16bit wide data path running at half the clock speed of AGA. Since a large part of AGAs benefit was actually the 32bit data bus and the doubled bus clockspeed over the OCS/ECS system you'll lose whatever benefits you hope to gain by having it.

Just my opinion obviously.

Andy

I'm just trying to make sure the Minimig is good VFM (at least as much as possible) by ensuring we think about features the design may need in the future, rather than designing a new board that will hinder growth. Would a CPU Fast Slot really not help AGA? Using my limited knowledge, I figure since the slot is 86pin it could handle a 32bit data bus. I could be wrong.

AJCopland said:
Basically take the A1200 as a minimum spec' for AGA and upgrade the MiniMig v1.1 to it.

I like this idea.

I would just like to state that there's plenty of mileage left in the v1.1 design for improvements (ability to write to the MultiMediaCard being #1 in my opinion), but the next revision of the PCB should be more ambitious.

[HenryCase]

downix wrote:

HenryCase wrote:
Downix, how many pins does your A500-like expansion port need?

92, but I wasn't using "pins" but a card-edge.

92, a fair few then! :crazy: :-D
I should have asked a little clearer, but I was actually wanting to know how many I/O pins from the FPGA (or 68000 CPU) your design uses. Could you break that down for me?

freqmax wrote:
Just want to point out that Xilinx Spartan-3 (like XC3S400 and XC3S500E) can do 622 Mbps transfers via a single I/O. So a 2x FPGA board won't need a staggering amount of fpga2fpga lanes.

Awesome, I was hoping this was the case. Is the transfer speed affected by FPGA complexity?