This is mostly a question/proposal aimed at the FPGA and PCB guys around here.
Looking at the original Amiga block diagram, one can see that ROM and FastRAM are connected directly to the 68k processor bus. On the miniMig design these connect through a multiplexed bus, thus sharing bandwidth between chipset and CPU.
Now, considering that the whole 68k CPU bus is externally available, how about putting 2MB of real FastRAM on the CPU bus (and adding an expansion connector in the process)? The ROM image could then be moved to this region of memory as well. This would allow the RAM to operate at CPU speed rather than at the current chipset related speed.
From my knowledge, I would say that this should happen following such a mod:
1. Over-clocked 68k should run at full speed from FastRAM without having to wait out on the chipset.
2. Full 2MB chipRAM.
3. ROM access will be at full speed.
4. RAM timing will be more relaxed with possibility to use 12ns RAM and maybe slower without effect.
5. CPU expansion bus?
6. CPU clock which is not a multiple of the chipset clock, just to get that last ounce of over-clocking potential.
Seeing that the miniMig platform is picking up as a generic simulation platform, there should be the option of disabling the 68k while leaving the RAM operational.
What do you guys think? Wouldn't it be a nice V3.00 miniMig? (I'd call it miniMig 300...)
Edwin
