I have just made some progress with planning and documentation reading. I am now concentrating on the memory controller part and found out that indeed it is not difficult to connect a 64bit wide SDRAM to the 32bit CPU bus. SDRAM modules use mask pins (DQM) with which you can easily mask out the upper or lower 32bit data based on address.
I was wondering when you notice that ;-)
Anyway, another way of doing this is to connect the 64 bits to one 32bit wide bus.
and switch the control signals. But, SDRAM is not the way to go anymore ...
To slow.
1. Using PC133 SO-DIMM memory modules (1 maybe two SO-DIMM slots)
2. Supported RAM modules 32MB,64MB,128MB,256MB,512MB which gives in theory 1GB max memory with two SO-DIMM slots. These modules are very cheap nowdays as second hand.
3. No burst mode due to lack of L2 cache. Next design will have 128K L2 cache.
4. 3.3v board using 68060 CPU
5. One old FPGA for 5v interfacing with Amiga, one new FPGA for memory controller and additional interfaces
6. possibility for future extension with 10/100 ethernet and USB 2.0 support on 2nd FPGA.
7. written in VHDL
to 1 & 2) If it has to be cheap, use on SO-DIMM. Also is much nicer to design cases it the long DIMMM Modules are not standing up, just as a reminder. Could be a nice flat board.
Personally, I would solder the RAM to the board. Less headaches with different versions of so-dimm modules/manufacturers
to 3) Careful ! You're missing something again. CPUs burst all the time, and you wanted to have an AGA in it to, right ? Yust make some calculations how much bandwidth you need and how much you get, using single accesses ...
(Entertain yourself with the 1600x1200 true color screen, and a 100 MHz CPU)
to 4) WHY ? You have a wonderfull big FPGA on board already. Why not use it ?
to 5) Big, expensive FPGA for CPU/MEMCtrl/VideoCtrl), the second for I/O is good. You actually run out of I/O pins very fast on those designs.
6.) Agree here, but put in on board already. People who design enclosures will love you ;-)
7.) Yes, however mixing Verilog/VHDL is not such a problem anymore.
Just my 0.000005 Cents ;-)
BTW, you just designed the Replay Board again, from
http://www.fpgaarcade.com
