Assembled Minimig v1.1, larger FPGA (BGA-package)

[ThomasML]

I'm making a new PCB layout based on the v1.1 schematics, and I'm wondering how many would be interested in this. My plan for the design is this:
* Add the slightly larger BGA-version of the FPGA (173 IO pins instead of 141).
* Make the board be 12cm x 12cm (to meet nano-itx requirements)
* Equip the board with pinout headers instead of the various connectors to make it easier to adapt to any casing.

I'm still asking around at various PCB manufacturers for pricing on manufacturing and assembly, so I don't know any price yet, I'm hoping to have it by the end of the week, or early next week.

So the part where I need feedback (in privmsg, I would prefer):
* How many assembled boards do you want?
* Do you want a kit with pinout -> connector for all the connectors that's on the current minimig-design?  (I'm trying to figure out if enough people want this to make it part of the package I should send off to the factory)

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Thomas

[ThomasML]

Hans_ wrote:
Seeing as you're making it nano-itx size, you might want to have a look if there are any standard nano-itx connector layouts you could use. With mini-itx there are standard layouts (or at least a standard backplate area that you can use). If you do go completely the pin header route, please use the standard pin header layouts for things such as the serial port; it'll make connecting them up so much easier.

There's hard to find any white papers about the Nano-itx. Via has white papers on mini-itx and pico-itx, but nothing on nano-itx, so I've looked at motherboard documents to see where the mounting holes needs to be.  I'm definitely going down the pinheader route, so no need to worry about matching the backplate, and I'm also going to use standard layouts for the serial-ports, for instance.

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Thomas

[ThomasML]

AJCopland wrote:
Couple of questions:
What will you do with the unused pins, bring them to an empty header/pin array for expansion?

Yes, I'll route them to a pinheader array so that they can be used for whatever people like.

Are there any other differences between the BGA and QFP versions of the FPGA?

Not much besides more IO-pins and some extra dollars in cost, no.

[/quote]
PS: I'd also be interested in an assembled one, have already said I'd take at least one blank board from Xenepp so will honour that request as well.
[/quote]

This is why I was a bit reluctant to announce this, I wanted to get feedback from Xenepp first, to make sure he didn't end up with a large batch of blank boards.  But, I haven't heard anything from him yet, I am afraid :-(

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Thomas

[ThomasML]

freqmax wrote:
@ThomasML:
I think you have to measure some existing Nano-ITX board :-)
(when via.com documentation is so nonexistant)

There are infact two "standard" layouts for the serial-ports (DE9).

I'm leaning more and more towards using pinouts on the board, actually.  This will be the most flexible option (make two diff. layouts is too expensive :-(  )

Maybe we could arrange the RAM_xx signals in order for the v1.1 board aswell?

Anything special you have in mind?

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Thomas

[ThomasML]

Mikkel wrote:
Why not go with an XC3S500E instead of the 3S400? It's cheaper, has more logic cells and is newer, so probably available longer.

Unless the 3E is missing some features that the 3 has, and that's used by the Minimig, I don't see any reason not to choose the XC3S500E for the design.   Good catch :-)

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Thomas

[ThomasML]

freqmax wrote:
@ThomasML:
I don't suggest making two version. Just that you pay attention to which PinHead<->DE9 wiring scheme you will use.

Ok

As for the RAM_xx signals, just look at the current wiring:
http://www.opencircuits.com/Minimig_Board_v1.0_FPGA_connections
I think that if the signals are A0, A1, A2, A3 etc.. routing will be much easier and electrically sound.

You're thinking about where the RAM-signals physically connects to the FPGA-package?

If you go for the BGA route. I suggest you have the pcb board DRC checked at fab. And the FPGA-BGA assembled aswell at fab. However the rest people could do by themselfes.

My plan was to get pricing on the fully assembled board (and that includes checking, but I'll get a quote for only assembling the BGA-package as well, but I think most people would want a fully assembled board).

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Thomas

[ThomasML]

Belial6 wrote:
OK, maybe this is a stupid idea, but what about having the BGA FPGA put onto a daughter card, so that other revisions of the MiniMig could use the same FPGA without the BGA worries?  Are the electrical tolerances to tight for that? :crazy:

I'm not going to put the FPGA on a sep. card, no, that would be to expensive, I'm afraid.

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Thomas

[ThomasML]

Belial6 wrote:
Is it only a cost issue, or is there a technical reason?

I do understand that cost matters, so I'm not trying to persuade you to change your mind.

It's perfectly doable to stack FPGAs, and I'm looking at adding a set of connectors to be able to connect more FPGAs to the design by making daughter-cards with the right set of connectors.

But making such cards is on of the tasks that should be on the todo-list, rather than on the "to get it working in the first place"-list.

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Thomas

[ThomasML]

freqmax wrote:
Yes.
Less vias => cleaner design => less emi etc..
And easier to track wires if the need arise.

This is how I'm suggesting that the layout will be:




Feel free to comment

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Thomas

[ThomasML]

jkonstan wrote:
Did you rebuild the MiniMIG Xilinx ISE Project with the new Spartan3E part/BGA package to make sure that new pin out would route (i.e. is the resulting pinout from Xilinx ISE floor planner)?

No, I'm pretty sure it'll route well, but I'm about to install ISE and compile it now.  Will let you know if there's any suggested changes from ISE.

The FPGA I've chosen has 1200k gates, tho, so it's a bit bigger than the one on the minimig today.  It's also large enough to fit a 68k inside the fpga.

Also, please see Xilinx Spartan3/3E APP notes on BGA 4/6layer PCB and on SSO (Simultaneous switched outputs).

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?iLanguageID=1&category=Publications/FPGA+Device+Families/Spartan-3E/Application+Notes
Check Xilinx XAPP689.pdf
Check Xilinx Xapp489.pdf

Yeah, I'll make sure to read those when I'm done with the schematics and starting on the pcb-layout.  I've been altering a few things more than once lately, as I've been talking to Dennis on email and getting a few ideas here and there :-)

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Thomas

[ThomasML]

AJCopland wrote:
lol well i can't comment on the technical side of it but it looks like all the main blocks I can identify are there. You'll have 10 user_io pins left. All 16 of the CPU address and data lines, likewise for the ram.

Actually, there's 10 user input-pins left, and 38 user input/output-pins left.  So, a total of 48 pins left for fun and expansion.

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Thomas

[ThomasML]

jkonstan wrote:
Thomas,

Please connect the MC68SEC000 Berr* pin12 to one of those  FPGA pins.

That's marked as VCC in the schematics I have.  Is that an error?  Should it be on one of the Input (or Input/Output) pins from the FPGA?

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Thomas

[ThomasML]

jkonstan wrote:
Thomas,
Please see this Open Circuits MiniMIG link where I explain why Berr* would be a nice to add back into the design.

Ok, I'll add map it, it's not like we're running out of pins or anything :-)

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Thomas

[ThomasML]

freqmax wrote:
While doing BGA, a switch to DRAM would also make ram cheaper and larger.
With DRAM use + HDL cpu an ordinary pre-assembled 200 USD board can be used..

What kind of pre-assembled board are you talking about now?  You mean we could use any of the starter kits instead of doing a custom board?  Or, are you thinking that one could use the starter kits if one doesn't want to buy a custom board?

I also found flaws in my fpga pinout, I was missing some pins, so I've floorplanned it inside ISE now.  Will publish the new suggested floorplan tomorrow.

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Thomas

[ThomasML]

freqmax wrote:
Yes, one could use pre-assembled ready to use developer boards. The only major obstacles is the physical CPU & Static-RAM.

They're larger and contain stuff you probably don't need tho, but it would serve a purpose of course.  In the end I think one would want custom boards tho, to be able to make the device smaller or just have all the cool stuff developed along the way, on one board.

But right now, we don't have anything besides a few schematics and nothing for mainstream to play with.  And the boards you're talking about is a bit more pricey than most people would like, I think.  (I'm not most people, I've already got digilents V2Pro-board  :-D  ).

So, what do you suggest we do?   I don't need to continue this work if it's not needed (don't take this the wrong way).   What one could do, is to make the board like it's now, with the extra user io-pins and everything, and continue developing the soft 68k and adding dram as an expansion.  Some day down the line one would maybe end up with a working solution, but right now we only have the proven minimig-design that works.  And we all know there's other work to be done to it, besides just the cpu and ram.

Any thoughts? :-)

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Thomas