Hmmm, doesn't x86-64 allow you to treat registers as halves, upper and lower, so any logic/arithmetic operations would be 32bit in the respective halves (with overflows etc)? Or am I confusing it with ordinary x86?
If I'm right, you could pack two 68k registers (perhaps just the 68k address registers) in a single x86-64 register and that would definitely confer a speed advantage.
Maybe this register sharing sounds good in theory but it's not so practical in practice. In general with both 68k and x86, there are no instructions to operate on the upper half of a register so this data has to be swapped to the lower half of the register, do an operation and then swap back to the upper half (approx. 3 instructions & 3 cycles). Maybe it wouldn't be so bad if the data in the upper half was less frequently used but accessing cache can sometimes be done in 1 cycle with 1 instruction. Samurai Crow has suggested somewhat similar techniques of register sharing for a 68k compiler. That is also limited but there are a few cases where it may be practical. A boolean variable can be used in the upper half of a different 16 or 8 bit variable in a register. Some newer processors like the 68060 can make some internal optimizations when operations the size of the register are used. In most cases it's just not practical to share registers like this.
Edit: Heiroglyph beat me to it
