i think for starters and for a600 in particular a limited softcore without fpu is enough. good news though that the apollo features fpu.
The current FPU is sparse like the ColdFire FPU but with fp immediates and maybe pre-decrement and post-increment for FMOVEM. I would like to see a more robust and 68k compatible FPU. Some think an SIMD will replace the FPU as happened with the x86/x64. Some of that happened because of limitations of the x86 FPU and it's sharing of the registers with the SIMD. In our case, the FPU is needed to do the more common double precision operations that compilers need as an SIMD would be single precision float only.
are there any vector instructions or what?
There is an SIMD unit but it's also not complete.
im not sure what would be the gain of adding coldfire instructions. by all means do not create another incompatible target software would have to be compiled for. the different versions for different 68k cpus are already annoyance enough. we need unity and common goals, not another split.
The ColdFire and other CPU enhancements are mostly aimed at improving code density and modernizing functionality. Defining a new ISA also allows some old instructions and addressing modes that slow a modern CPU to be deprecated so slow CPU traps/exceptions are avoided in new code. The 68000 or 68020 would still be a compatible base and the more common compiler target. There isn't much point in the mini-Apollo (Phoenix) CPU having CF instructions as there will be no ISA to support them but they are practically free. Maybe some support code will be able to make use of them.
Majsta's future hardware creations (probably for AGA) will likely have a significantly larger fpga. It's a tight squeeze fitting a fully pipelined CPU with caches into a Cyclone 2. A larger fpga would allow for a much more powerful CPU with FPU and SIMD.