Even though having the flash at $0 is pretty much fatal I checked with this [http://piru.dyndns.org/~p/coldfire-v4-m68k.txt] coldfire->68k missing features list to find out what to check for. I figured Coldfire is so cut down that compared to CPU32 nothing else would be missing, someone else with far more patience should be able to find more incomplete features than I could.
I assumed the addressing modes were correct and didn't look into this much as the guide doesn't list any definite info. (It references 'core addressing modes' but links to nowhere, plus the m68000 reference guide doesn't explicitly say that CPU32 does not have every addressing mode the 68000 does.)
*Opcodes missing sizes* - All OK
*Completely missing opcodes* - Some exceptions
There are only 5 BCD instructions, The Fido has the original '000 ABCD, NBCD & SBCD but does not have PACK & UNPK which first appeared in the '020.
All the bitfield operations that first appeared in the '020 (FCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET & BFTST) are not present.
(From the Motorola M68000 Family Programmer’s Reference Manual - section 7.1)
''The CPU32 can execute object code from an MC68000 and MC68010 and many of the instructions of the MC68020.
There are three new instructions provided for the CPU32: BGND, LPSTOP, [TBLS, TBLSN, TBLU, and TBLUN]).
The MC68020 instructions not supported by the CPU32 are BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST, CALLM, CAS, CAS2, cpBcc, cpDBcc, cpGEN, cpRESTORE, cpSAVE, cpScc, cpTRAPcc, RTM, PACK & UNPK.''
So to me it appears that the Fido could function as a souped up 66Mhz 68000 but other things that still are a mystery are;
* Freeing up of location $0 - I don't think it is possible to get the Amiga to mark the first 1M as 'do not use' seeing as it is meant to be chip ram? Maybe if the Kickstart was modified and only system friendly apps were used but whats the point of it if no games will work?
* No floating point unit - Can a 68881/2 be added, there is no mention of it in the user guide.
* External interfacing - The pin outs are odd, full 30 bit address bus but only 16 bit data bus. (plus SDRAM refresh logic is built in?)
* The extra features such as built in ethernet could be useful, what would be more useful would be configuring the UICs to become the extra 16 bits of the data bus.
If someone could get their hands on one they could make a board and get it to replace the cpu on an a500 just as a test. It says it is 5v tolerant so it could (maybe) work if the addr $0 problem can be resolved.
