Accelerator hardware theory

[Gulliver]

I have an A600 and a spare 68030 micro, so i though i could figure if it is feasable building an accelerator card for it.
Please do correct my assumptions and clarify my doubts if possible!

Q: How do i stop the 68000 from working?
A: Using the HLT pin i can let the other micro get control

Q: How do i synchronize the accelerator micro at eg 25mhz with the 7 mhz A600 bus? Can i overclock safely the A600 bus?
A:

Q: 68000 is 16 bit externally, 68030 is 32 bits. How do i join data signals?
A: I guess i shoul join the 16 bit 68000 data to the LSB of the 68030. Dont know!

Anyway its a hobby project, and to keep it small and simple, and cheap, i wont put ram or a rtc on it.

[Gulliver]

I thought abou waitstates but i found several designs claimed to have Zero wait states! How? I dont know!

So, ATM the only solution regarding bus synchronization would be to acces the A600 bus according to its 7mhz clock rate thus providing a great performance penalty not to use the accelerators speed.

[Gulliver]

I am also waitin for Schoenfeld accelerator, but anyway i would like to know how to build one.
Of course an accelerator without mem is a huge penalty! But i wanted to do one thing at a time, first learn how to properly accelerate an Amiga and then add all other beauties such as Fastram, RTC, Local bus expansion etc.
It is easier doing it little by little, than attempting to do it in one shot.

Yep 68010 is better than 68000, but 68030 is far better!

[Gulliver]

Thanks for pointing me that out billt!
Any suggestions, ideas, criticism?

[Gulliver]

Thank you guys, I will defiately take your recomendations, those were the kind of answers i was hoping to get.
Big thanks! :-)

[Gulliver]

Will use an A600 because i have one! I dont have an A500, but then its the same bloody micro with a different layout, so in theory it would be dead easy to use one or the other.
On the other hand it is a hobby project, not a commercial venture. The reason is simple, i love electronics and Amigas, so i was in the hope i could learn something by building the accelerator. Of course i would like to add an IDE interface FASTRAM, a local bus expansion for other add-ons, but then trying to accomplish so much from the start will probably end up in a pipe dream, and will make me fail in achieving my main goal: building an accelerator.

[Gulliver]

@Unit01
Thanks, I will look into it!

I am just sorting some things out, and polishing my knowledge on the design.
I will get back on you with my findings!

[Gulliver]

I thought a little more about my A600, my accelerator, and made my own mind about some things:
I hate SMC designs, they are not for hobbysts
I dislike ICs which are not DIL for the same reason
So what the hell was i doing with an A600 in the first place! I will try to find an A500 and continue work with it. It is so much easy to hack! Anyway as i mentioned before it is just a different micro layout, and Schoenfeld is about to sell his own, so i dont want to infringe any damage as little as it coul be, to his company!
I made up my mind: an A500 on-chip accelerator, will fit with no troubles many Amiga models as some of you have stated previously (A2000, A1000, A1500, etc).
I read about the Lucas accelerator and the Frances memory board. Too much interesting mental notes were taken in that process, and i eventually could draw some conclusions about my own project.

Even though, i need some help here!

68000 to 68030 interface:
As stated in the Lucas accelerator project, the idea is to make the 68030 resemble an 68000 at 7mhz to the amiga system bus. However, both microprocessor are not pin to pin compatible and have a few different control signals not to mention speed. So this is the actual challenge!
Differences to be solved:

1- Different clock rates
2- Data and Address signals
3- Bus length,/DTACK vs. /DSACK0 and /DSACK1
4- Byte addressability, /UDS and LDS vs. /DS
5- E clock generation at 1/10th of clock signal (0.7mhz)

The help i need is regarding item number 4. In the Lucas accelerator some PAL equations are mentioned, which i dont understand. However, these signal conversions were done in  a PAL, i wish someone could point me in the right direction, so i can make them with 74xxx logic ICs.

I have allready covered all the other items mentioned, i wish you could tell me if there is something else i am missing here!
:rtfm:

Thanks