So you comparing a 8086 to Power1? Intel back at time didn't apply RISC techniques to their CPUs.
Actually I'm talking about the PowerPC 601!
“Energy efficiency” was a recent re-positioning for the said product.
But it has been the last few years due to targeting the embedded market and has been the primary focus of IBM (and even Motorola) until now!
It would be pointless since the current G3 and G4 communicates with the out world side @133Mhz.
Why would you not increase the bandwidth around the CPU if the architecture allowed that possibility?!
Secondly, G4 has a massive 512kb L2 cache to compensate some of the problem e.g. OpenSSL's core routines should fitting nicely.
The Pentium 4 has 512kb L2 cache as well!
Note that Athlon XP has yet to have the 512 L2 treatment unlike the G4.
Yeah but the Athlon MP is the only one that is designed with its memory cache cross-strapped... I think that's a great advantage!
Are you implying that AmigaOne HW can mount IBM’s new chip?
Well unless EyeTech has changed its CPU strategy, I am assuming the G3s/G4s will come as expected!