ColdFire Project?

[rkauer]

 I think the best solution for the Coldfire instruction set issue is adding a parallel "small" Spartan to catch the instructions who are not compatible with 68k.

 That could be a way to fix all problems in a snap.

 Then we get the best of two worlds: the speed and low cost of  a Coldfire (compared to a 060) and the complete set of 68k instructions, with no issues.

 My two cents.

[rkauer]

Piru wrote:

How would that work exactly? How can some external chip know what the CPU is doing?

 I mean use a Spartan as a translator table to catch the instructions the Coldfire can't process in the right way. Indeed it will generate some slowdowns, but in the end we can get an operational CPU who behaves like a 060 ~44MHz, who is a major upgrade from old accelerators around (I mean 030 and 040s).

[rkauer]

Piru wrote:

But how can you do that? How can you make the spartan interface with the CPU in such way?

 What I think is only a well-intended guess.

 This is almost the same as a PPC board acts. Those Spartan CPUs have near the double IO pins as the 68k CPUs, so is not a big worry in the hardware connection, but must be a worry in SW (I think a nightmare is the correct word).

 The voltage level is the same, clocks can be decoupled, instructions can be interpreted BEFORE trowed to Coldfire...

 My 2 cents...