ADOOM on A600 running 22-35 FPS

[biggun]

Mot made a choice with these restrictions. The reason why d(PC) and d(PC,Xn) is read-only is a good one:

Of course I can also see the "idiology" of MOTO behind it.
But lets also look at the reality.
During the project we did disasm so many programs and looked wwhat they do and how well the CPU can do it.

There were many programs programs doing this often and very often
lea (d,pc),A0
addq.l  #1,(A0)

So if a programmer or compiler decided to update local variables in such a way
and does this 1000 times in his program - then so be it.
With the old address limitations he can still do it. But the programs executed 1000 instructions more, and is 2024 Byte bigger.

[biggun]

As far as I know an 040 and 060 has a single branch to execute floating point operations. If you had three branches or more would you get some seriously fast math operations. If not what would limit it?

68060 FPU was not pipelined and most instructions took at least 3 cycles.

Phoenix FPU is fully pipelined and can do a 80bit FMUL every clock cycle.
This means clock by clock the Phoenix FPU is already 3 times faster than an 68060.
This means a 100 Mhz Phoenix is FPU wise in theory as strong as an 68060 @ 300 MHz

[biggun]

Matthey,

the amount of "voting" to the project is in level to their work contributed.
There are some people who have contributed some hundred thousand lines and some which have not.

[biggun]

@olaf
Why? Matt is helpful, constructive and concerned person. Mentioning doubths in the open isnt wrong.

The situation is that hardware developers which do _all_ the development work on the core
and which have CPU design and FPGA know-how have certain opinions
what features should be implemented, and which features are sensible to do in an FPGA.

People from the outside can voice their opinions this is OK.
Its also OK that they voice their opinion if they have no FPGA knowledge.

But the decision of what gets implemented is done by those who do the work.

[biggun]

Then ThoR would have had no vote either

Of course Thomas Richter has a vote. :-)
Thomas did contribute to the project and we value his opinion.


At the end the people doing the work will make the decision. I think this is normal.

And as MP3 playback and DOOM and other programs show..
The software Compatibility and Performance are good.
In fact the performance of Poenix is better than any 68K CPU was ever before.

[biggun]

Apollo is much bigger than it appears to many.
The project does not only include CPU but also FPU and SIMD features.
A lot of planning and over 5 years of development were put into this project.

The current FPGA cards show a small part of the project.
The upcoming FPGA cards will show a lot more....

[biggun]

To really interested I'm happy to explain the advantages
and reasons behind certains ISA differences.
Also in the context of what is possible or of advantage in an FPGA versus ASIC design.
And also in the context of what considerations or differences todays cache or memory interfaces have.

I think there here might not be the ideal place for explaining this.

If someone is _really_ interested in learning about this, brainstomring or discussing this topic,
then I invite you to go to the forum on http://www.apollo-core.com. I'm happy to give explanantion, data, and real live measurements for you there.

[biggun]

Maximum FPGA optimization involves combining units but this is a bad idea as it becomes more complex and an ASIC becomes less likely.

interesting interesting.

You are aware that the people who have developed the APOLLO work as professionally FPGA and CPU designer, don't you?

You know that some of IBM fastest Accelerators and latest POWER chips were desinged by those people.

[biggun]

@ Matthey
Could you tell us why you need an ASIC so badly? There is only one coldfire accelerator card for an Atari.

This is all bollocks spread by one person.

There is nothing technically in APOLLO which prevents doing an ASIC.

[biggun]

 The implication was ....

Facts are:
 * Phoenix is working,
 * People use it
 * Phoenix is the most technical advanced and fastest 68K CPU ever done by men. :-)




I find this "barking" quite amuzing. :-)

When Phoenix was talked about many people wrote that
* Phoenix is not real and that we are just lyers.



Now people complain about this and that feature.
Funnily these people have never  used Phoenix, never seen it, and do not know how Phoenix really works.

Matt seems to be a big fan of Phoenix as he is so kind to explain people in forums
all over the place how Phoenix does this or that.
But mind that  Matt has his  knowledge only from interpreting my posts in the Apollo Forum.

This means his  explanations often contain some misunderstandings and also outdated info which was changed long ago.

Its nice that Matt advertised for us.
Thank you Matt.

But please mind with all his explanations that Matt does not know the Phoenix sources,
and that he never had seen or used the Phoenix in real live.
So all information is hear-say from reading our forum...

If you want 100% reliable information then the best idea is to ask the people that know directly.

[biggun]

Does it contain any new instructions that I can use to produce the World's Best 2D Strategy Board Game(tm) ?

Have you left away any instructions that you are saving for the rumored future A1200 Apollo card?

I don't care if certain compilers don't "support" the new instructions.  T

The best place to ask this and get detailed information is

http://www.apollo-core.com/knowledge.php

If you have problems or urgent questions then the IRC channel is a place to get help.


In short answers:

Yes the core supports new instructions
Yes, the core supports more registers, or more flexible usage of old registers
Yes the core supports more flexiblel EA-modes
 The core has a number of automatic performance enhabcing features
like e.g. streaming, prefetching, dual ported caches etc.
In addition to this the developer can use new features.
Like Branch Misprediction prevention
Like Parallel Memory Loads
Like Cache control

Even without using the new features the core is faster than any existing 68K core.
But using the new features will give you more.

[biggun]

Frankly here was quite some non-sense posted.

The A-line extension to NOT clash with ATARI or APPLE or any other old A-line usage.
Matt what you say is just technically not true. You should know this better.


Also you did say that the FPGA Vector implementation would prevent an ASIC version of the core.
As the way the Registerfile they way Apollo does it  would not be good fro ASICS.
Again that is technically not true.

The latest and world fastest ASICS on the market use a merged Regfile just the same way as we do.
So this prooves that our solution is working perfectly in an ASIC and in fact is "state of the art".

Matt, we are very happy to discuss compiler optimizations ideas.
Technical ASIC/FPGA discussions should be done by people understanding them fully.

[biggun]

Technically it should be possible to make an ASIC .

An ASIC always sounds nice.
But I think that using FPGA has lots of advantages too.

In an FPGA you can test and evolve the design over and over again.
The Vampire 600 FPGA is not big, and when we started the port
of Apollo to it, I was not sure that we could fit much of Apollo in it.

The FPGA allowed to tweak, tune, and optimise the design.
and now we have 68020 software support and still not to bad performance and all this in this small FPGA.

This shows the big advantage that FPGA give you for development.
You can tune and tweak and develop 100 evolutions of a design.
Producing 100 ASIC evolutions would have cost a fortune....

Low end FPGA are not costly.
So the ASIC has not even  price advantage to very low end FPGAs.

The only real advantage on an ASIC would be speed.
Sure with an ASIC we could dream of reaching a gigaherz ...

But we are not there yet - we need a lot more time to develop our ideas.
To test the SAGA chipset etc.
And for this FPGAs are really great.

[biggun]

Technically it should be possible to make an ASIC

I really wonder if it makes sense to make an ASIC.

In the V600 FPGA we see an average performance of ~ 200 MHz 68020

Our expectations for the next card is a performance about 3 times higher
e.g ~ 600 MHz 68020
And the card will still be very affortable compared to 68060 cards.

Not if we would spend money on a fast FPGA - like people spend money on 68060 cards.
Then we could again double the value and reach a performance on a ballpark of over a Gigaherz 68020.

Do we really need an ASIC?

[biggun]

The Phoenix core offers excellent performance/price for Amiga hardware.

Thanks
 

An FPGA is too expensive to make it cheap enough for mass produced hardware like the Raspberry Pi

What would be the pricepoint in your opinion for the FPGA/ASIC?

Lets say we wanted to build a new retro AMIGA with 600 MHz 68020 performance, fast FPU
256 MB fast memory, SAGA (truecolor) chipset ...
What in your opinion is the price break for the FPGA of such a system?
At which price you would say the FPGA is ideal for this?

[biggun]

Looking at current FPGA stand alone boards, we see a price of $200-$300 U.S. for good quality boards with low to mid range Amiga specs. .

you compare apples and oranges.
The current FPGA boards for AMIGA have quite  high prices for what they offer.
That these board have so high prices DOES NOT mean that an FPGA is more expensive than an ASIC.

An FPGA board with 256 MB fastmem, and 68020 CPU with 600 Mhz performance and SAGA could today be sold for less than $100. If a few thousand would be produced.