ARM or x86 with FPGA emulator

[biggun]

Or maybe POWER8 monster so expensive, that hardly anyone can afford it, where using more than 1 core or more than 2GB RAM

The Power8 box, that I daily work on has 4 Terra byte main memory :-)
Now what?

[biggun]

So what? How much did this Power8 box cost?

Over $100,000

And yes this box is big and has 80 cores , and _no_ Amiga OS does not support it.

There a big POWER machines build today and also bought for a lot of money.
So POWER is by far not dead.


What your interest is in "very small" machines.
And yes in this segment there are currently not really POWER offerings.
All new POWER systems that are sold in the last years a real big systems.


But POWER is now "open".
You know this right?
This means "Mr Chinese company" could take a POWER Chips design today
and tomorrow sell a POWER based laptop, or netbook or what ever.
This could happen or maybe not - I don't know - you don't know.

What I would not do here - is running now around and tell the people that build hardware for a living - what they should do.

Believe me the people have choosen PPC for their systems for a reason.
Whether this reason is valid today - maybe - maybe not.
But anywhich way these people will be totally aware of all this.
And do not need yours or mine advice.

So save your breath... You will anyway not change anything with it.

[biggun]

He has a point that there are no POWER-PC offering in the "user-price segment".
IBM does produce very good POWER chips for servers in the price segment of $20,000 and plus.
But there is a "hole" in the user segment.

You can go out and buy a good x86 Laptop today for $500
You can not get a PPC laptop.

Of course talking here about it will change nothing...



If you compare it with cars then
* IBM is selling FERRARIS
* AMIGA hardware are fast as a FIAT-PANDA but are sold with a price tag of a Ford Mustang.

Its understandable that users would prefer to pay either FIAT-PANDA prices for PANDA performance
or they want at least Mustang performance for the price the pay.

[biggun]

PowerPC is not a bad architecture but it has lost the race.

Its very simple...
There are two main companies building POWER/PPC CPUs.
These are IBM and MOTOROLA aka FREESCALE.

IBM is _only_ interested in the high end server market.
Therefore they only produce high end servers.

Freescales PPC customers are telecom/router manufacturer.
So Freescale of focuses on producing chips which are ideally suited for there customers.


Doing a CPU development costs roughly about $50,000,000 USD.

Neither IBM nor Freescale have any customers using the PPC in the desktop / home -pc market segment. So taking a lot of money and building a CPU for no customers - makes really no sense to them.

The Antaris aka 970 aka G5 CPU was a desktop version of the IBM POWER-4 CPU.
Since then no desktop-CPU was build.
But IBM did continue to improve the POWER chips,
After POWER4 came POWER5, then POWER 6, then POWER 7, and now you can buy POWER 8.
So IBM did improve the POWER continuesly. And continues to do this.
But in the "user" segment you do not see this.

The same is with Freescale. Freescale continued to improve their PPC offering -
but in the market segment which their customers did demand.

[biggun]

Both MIPS and SPARC have open designs, which means A-EON could improve them without a license.

Are you aware of "OPEN POWER"?

[biggun]

Why do we talk about this so long ?

Everybody with some "brain" sees immediately that moving to SPARC or MIPS would be no improvement over PPC at all.

* The Compilers for SPARC or MIPS are not any better than for PPC
* You would loose all existing PPC code. 68K to PPC Jit etc
* SPARC and MIPS are not faster than PPC
* There are no more or no better chips available for users


Is a silly proposal

[biggun]

Currently there are plenty of more performant MIPS and SPARC chips available than most PowerPC gear. The R16000 of MIPS fame is faster despite being clocked lower, and a Sun Ultra 45 wipes the walls with a G5 and a PA6T. We're talking 10+ year old designs:

The Sun ULTRA 45 came our 8 years ago - while the G5 came to market 12 years ago,.
Whether a old  Sparc is faster than an much older PPC does not really matter.


The which AMIGA users migh interest is:
* being able to run existing software
* being able to buy good, new hardware for a reasonable price

PPC is least provides the first point.

[biggun]

I'm not being unreasonable and I'm certainly making a point that everyone seems to casually deny: that SPARC and MIPS are readily available, and offer more performance for less cost than our current designs.

Please show use where we could buy new Laptops or new Desktop with these for < $500.
If you can do this - then your would have a reasonable point.

[biggun]

Gladly for MIPS: lemote.com/en/products
.

What are the prices of these products?

[biggun]

Yes, I'm anti-x86. I'm against a backwards architecture that is poorly engineered,.

Big words ...
I would not look down on x86 as this "poor" architecture is a  super performer.

x86  also has some big advantages over MIPS and SPARC.
* x86 has good address modes
* x86 can use immediates in instructions directly
  This is a big plus
* x86 can directly operate on memory.

Your x86 CPU can with 2 instructions often do about the same work as your MIPS does with 4.

[biggun]

It takes about 40 cycles for the average x86/x64 CPU to access memory due to the size of the pipeline, a MIPS R16000 can do it in 11.

??
Where did you get these numbers from?
These are not memory access times.

[biggun]

Sure biggun, but it takes longer to have those instructions processed.

No actually not.

Thats the point.

The same is true of 68k/Phoenix.

Phoenix for example can do this instruction in a single cycle:
ADD.L #$123456,($40,A0,D0*

How many instrutions does your typical RiSK need for this?
Exactly what the 68K does in a single Cycle the RISC needs generally  5-6 instructions to do the same.

[biggun]

So? The fact is that while you can feed those into the processor all at once, it takes multiple cycles to do those instructions.

No.
PHOENIX can do this instrution example in 1 single cycle.
PHOENIX can do every cycle such an instruction.

Also let me remind you: memory is cheap now. We don't need a CPU that works direct from memory - working load/store is fine.

The problem is the instruction throughput.
Lets say you have a super scalar 68K.
Which does just 3 instrutions per cycle.

Do get the same amount of work done you need much much more RISC instructions decoded per cycle.
 And this is what kills you. You can not decode 10 instructions per cycle with your RISC chips.
Simply because your Icache is unable to feed so many bytes to you per cycle.
CISC instruction are a form of "compressed" instruction encoding.
This is a big advantage today - as today the cache bandwidth as a limiting factor.

[biggun]

CISC just doesn't make sense anymore and there is support for this in the simplicity of RISC. Look at anything else engineering related and you'll see that generally the simpler solution is better.

You repeat marketing slogans of the 90th.
These slogans are technically outdated today.

Some facts:
* CISC has stronger instructions than RISC

In the late 80th and early 90th making a simpler RISC decoders allowed
to invest this into other parts of the chip to improve performance.
As this time RISC chips had a performance advantage.

But technology moved on...
The decode is NOT the bottleneck anymore.
CISC chips can today decode the same amount of instructions as RISC chips.

Today the most complex part and biggest parts of the CPU are the Caches.

Today the main challanges when designing a CPU are:


1) Resolving Instructions dependancies.
CISC has here some advantage - as a CISC CPU an do more with less.

2) Cache access is the other big bottleneck.
CISC has here two big advantages.
* CISC instructions are much more compact. Therefore they can do more with the same ICache Bandwidth.
* The number of possible parallel DCache read and DCache writes
is today the real limiting factor today in CPU design.

As RISC chips lack by design real immediate handling - all RISC chips needs to do more DCache reads to do the same amount of work as CISC chips.


Think about the above technical facts and rethink your opinion about the RISC vs CISC discussion,

[biggun]

Of course, biggun you can always try proving me wrong by building this super orthogonal CPU and trying to benchmark it against a processor of the same application that is RISC. I'll be waiting.

Been there done that ...

http://www.apollo-core.com/