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Author Topic: Minimig worthwhile?  (Read 3851 times)

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Offline boing4000

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Re: Minimig worthwhile?
« on: March 23, 2009, 02:42:38 PM »
Minimig is the first step in open source simmulation of (any) Amiga chipset. It starts with OCS, is now nearly full ECS compatible and also could grow to AGA on different pcb.

You can find very much information in this forum by searching for "minimig" or just visit www.minimig.net for even more user and infos about this project.

PS: I do love Minimig because it started as a one man show (Dennis v. Weeren) and already has many interested user and platforms :-)
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Offline boing4000

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Re: Minimig worthwhile?
« Reply #1 on: March 23, 2009, 08:03:57 PM »
Quote

Darrin wrote:
UAE is a cheap imitation of Amiga hardware.  The Minimig is new classic Amiga hardware.  Currently Minimig v1.1 has 1.5MB RAM, ECS, 28MHz 68000, 4 floppy drives, PAL and NTSC modes, a scan doubler and hard drive booting OS3.1.  It makes it a cost effective A500 replacement for games.


Make that possible 3.5MB :-)

General:
Minimig and (any)UAE is not compareable to each other because emulation and simulation is a big difference! The fpga Amiga is a native simulator, no one will ever notice any difference to real Amiga(500/2000) on the same screen. Smooth scrolling and perfect feeling as on the real machine!

Of course I do understand in different interests. If one just like the real hardware, he may do so :-)
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Offline boing4000

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Re: Minimig worthwhile?
« Reply #2 on: March 24, 2009, 06:12:48 PM »
Take your time in soldering those RAM chips Darrin. Its of course possible but require a quiet hand and suitable equipment like: 0.7mm fine solder, desoldering braid (and if available solder flux). Also the upper RAM chips has to match pin grid accurately, else its hard to solder a stable contact.

If there is any problem, Im sure Jakub or I can help to make your BigMem-Minimig run :-)
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Offline boing4000

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Re: Minimig worthwhile?
« Reply #3 on: March 25, 2009, 03:44:22 PM »
Right, each pin #6 is not to bend. This modification will only work in new core release. Currently the extra ChipEnable lines should not be connected to spare IO pin, it could cause unwanted trouble.

It would be best to use removeable connection at spare IO due to some alternative FPGA core on Minimig pcb. FPGA64 and VIC20 core uses spare IO for Floppy IEC bus connection, This could interfere if suddenly some RAM enable went to low and cause a bus conflict.
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