@alexh
In my understanding VHDL is Verilog. There is also a HDL programming language. Xilinx Webpack can do both.
If you take a closer look to the .zip file, you will find this directory structure:
Minimig-29-05-2008
drwxr-xr-x 2 0 0 4,0K 29. Mai 02:24 build
-rwxr-xr-x 1 0 0 35K 22. Jul 2007 gpl.txt
-rwxr-xr-x 1 0 0 18K 29. Mai 14:03 Jumper.jpg
-rwxr-xr-x 1 0 0 320 29. Mai 14:34 readme_29-05-2008.txt
drwxr-xr-x 2 0 0 4,0K 29. Mai 14:30 source
So you can find the full FPGA sources AND binary inside the zip file.