Motorola 68060 FPGA replacement module (idea)

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I'm thinking on developing at least one FPGA just to try it out. And you can't have the core until you have a PCB nor can you have a working PCB test until you have a core

So one make a PCB. Then generate a core that just toggle bits and does basic bus testing. When that is complete. The next step is to code a 68k core.

Perhaps it's possible to run the 68k bus really slow like 1 MHz just to prove it works.

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Orignal problem: The FPGA Arcade has some 68020 hybrid. But the number of logic cells in the XC3S1600 is finite so any more fancy CPU has to be elsewhere. Now the solution mikej has accomplished is a daughterboard with a 68060 CPU.

However there's a small number of really fast 68060 CPUs and the numbers are declining. But if one use an FPGA instead of the CPU. One can create a replacement. And FPGA factors like type (Actel), blockram, HDL-code optimizations etc can improve the performance.

So the goal was to use it with FPGA Arcade. And A4000, A3000, A1200 etc is a bonus. A 68030 bus is a subset of 68060 so it won't provide 060 systems with a solution.

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Let's focus on the design rather than repeating the basics. Please?

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KiCad
(free and thus makes sharing easy)

Agreed, but so far I'm hearing we don't have the basics covered yet. No core, design no go. Even if starting with TG68... must compare were it is to where it needs to go.

I meant basics like that PCB consist of some serious routing issues. It's not like the wall socket. FPGA is not set in stone, is reconfigurable at least every 1/10 second etc..

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@A6000, If you get tired of 68060 you can switch to a 68030 in 1/10 second.. (with FPGA)

FPGA Arcade daughterboard with onboard FPGA is of course nice. My thought was that Arcade, A4000, Accelerator cards (A1200) could benefit from this in one go. And A3000 too with an adapter.

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68060 has some performance factors:
# 10 stage pipeline.
# Two cycle integer multiplication unit.
# Branch prediction.
# Dual instruction pipeline.
# Instructions in the address generation unit (AGU) and thereby supply the result two cycles before the ALU.
# Superscalar (asfair)

It's about being able to run the most ,m68k opcodes per second. I guess having "the best" m68k running the computer in itself perhaps is also a factor

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That issue is solved with a simple mechanical adapter, as already mentioned. The 060 socket has signals that 030 socket doesn't. So you can go down, but not up.

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I presume 16-bit branching is the same as that if a certain flag is set then one can conditionally jump 65536 memory positions?

I have some memory that x86 is limited to 128 position limit on branching? or perhaps it's 6502
How about ARM?

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@matthey, Nice insight!

Do you think it's feasable to create something that can get near 50 MHz 68060 in FPGA ?

I was thinking on Intel 80386 ISA in protected mode (kernel and user) regarding branching. As for 8086 and segments.. yuck

Is there any evidence to show they remap the opcodes at all? They might just store each opcode +operands within the fixed width fifo.

Perhaps another reverse engineering approach is to figure out from other parts what you need to make your duplicate to work.
A 68060 functionally duplicate won't have to be designed the same way. Just interact with software code in way that the original programmer intended.

Maybe the early decode just figures out how long each instruction is and whether the next instruction is valid to go in the secondary pipeline.

So there is a a kind of selection process such that instructions that doesn't depend on sequent instructions could be done in parallel while the rest is single pipeline?


Btw, Is there any ISA that is neater and more straightforward than m68k?

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I suspect there is no documentation except the usual datasheet

Perhaps someone could interview some of the original engineers?

What's a "Link stack" ..?

Have you looked at the Actel FPGAs?, they are way faster than any competitor last time I checked. Of course they are slightly more expensive.

As for ISA, my thinking were if the ISA of ARM, Transmeta, PDP-11, MIPS, Sparc, DEC Alpha, PA-RISC, etc is easier to deal with. Without sacrificing performance.

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Actually a default model could be to provide just a few instructions and have the rest as trapped instructions. That means one has something workable fast. Then one could make the architecture correct. And then add the full instruction set.

If one start with the instructions and then try to impose the correct architecture.. well it could be messy

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That's a big part of why "they" moved away from hardwired control units in favor of microcoded control units. My own education thus far was about hardwired style, which is very dependent on the instruction set. I was hopin gto take the advanced followup course now, but it wasn't on the schedule. I'm trying to go through the Coursera one now, which is pretty advanced. Not sure if they explain microcoding or if that assumes you already know it. Going to try and find some time to read up on it more regardless.

Microcode adds more clock cycles per instruction. Or at minimum latency.
(which will then impede clock increases)

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Which compilers even have an 060 option?

gcc version 3.3.3 has these options:
-m68000 -m68020 -m68020-40 -m68030 -m68040 -m68881 -mbitfield -mc68000 -mc68020 -mfpa -mnobitfield -mrtd -mshort -msoft-float

But perhaps SAS C has something more specific?

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I'm pretty sure the latest SAS/C does,

I would like to know what options SAS-C has

Anyway I checked out gcc v4.2.1 (slightly unsure on version) which has the options:
-m68000  -m68020  -m68020-40   -m68020-60  -m68030
      -m68040 -m68060  -mcpu32  -m5200  -mcfv4e -m68881  -mbitfield
      -mc68000  -mc68020 -mnobitfield  -mrtd  -mshort  -msoft-float
      -mpcrel -malign-int   -mstrict-align   -msep-data  -mno-sep-data
      -mshared-library-id=n  -mid-shared-library  -mno-id-shared-library

-m68060
      This option inhibits the use of 68020 and 68881/68882 instructions
      that have to be emulated by software on the 68060.  Use this option
      if your 68060 does not have code to emulate those instructions.

As the 020, 030, 040 options doesn't mention the omission of any instructions. It seems the 060 is the only m68k CPU to have less instructions than it's predecessors.

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Why were these instructions dropped?

And would be more efficient performance wise to implement a 020, 030, or 040 and then horrendously overclock it?

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Regarding instruction set (ISA) I was thinking in general why they changed it. Because the end result is a slight confusion.