Full 68060 implementation?

[freqmax]

Does there exist enough documentation and FPGA fabric size to make a full soft-HDL 68060 processor? and at full speed?  (preferably with Xilinx Spartan series, Virtex is expensive)

This could then be used to mitigate shortage, insane prices and make tweaks possible.

[freqmax]

I think functionally equalient is a good goal. But ASIC is no good. 1) It's darn expensive 2) Any bugs will be unfixable

[freqmax]

What about a less complicated CPU (68000/68020) running at a high speed (100 MHz)?

Already covered by MikeJ and his main developer.

But it could serve as a starting point.

[freqmax]

Perhaps they can be overclocked with peltier and fluid cooling? or even nitrogen for a few hours?

[freqmax]

Is there any software that use 68060 (or 030, 040) specific "features" that make them incompatible if the processor isn't cycle exact and uses the same behaviour?

[freqmax]

Is there any CPU specific behaviors other than what the assembler instructions specify. That any software is dependent on?

(Like instruction XX flipping register bit Y when in Z mode etc..)

[freqmax]

It goes further than opcodes. As the I/O connections and modes may screw around with execution behaviour, or even bus response.

[freqmax]

Have look at alignment issues for those timing issues. Especially in combination with pre-fetch (L-cache).

[freqmax]

Can one skip out-of-order execution, super scalar, etc.. and still run 68060 code?

What are the minimum feature set that has to be implemented? (albeit slow..)