FPGA Amiga's and Genlocks

[freqmax]

If you can feed the sync signal to one FPGA I/O pin and "recompile" a new core that makes use of DCM to scynchronise the 4x video clock, it should be doable.

[freqmax]

DVI/HDMI/SDI input shouldn't be rocket science. Except perhaps a rocketport for Xilinx FPGA