When will FPGA Arcade Replay Batch 2 be available?

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@MikeJ, Is the current memory controller too optimisitic regardning timing etc?

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I don't think the code has to be "perfect". Likely better to provide firmware that can be upgraded in the field and ship more rapidly.

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The memory controller has very relaxed timing actually and the performance can be increased. It needs to be a little more flexible in the IO timing as I'm seeing some differences between boards. I do memory controllers for a living, so it's not an issue.

How much difference is it between the boards? I guess it's the memory chip itself that varies and not the FPGA etc.

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Just trying to get a handle on how many % the timing differs within a batch of memory chips.