FPGAs implement the connectivity and logic gate setup that the HDL-code (VHDL/Verilog) specify. It will be slightly slower than a plain ASIC because the extra circuitry to make it possible to change function on the fly.
Thus the HDL-code specify connections and gate setup. The only exception are special builtin blocks that deals with phase locking, I/O modes etc.
It won't emulate, simulate, run any code or anything else. All that is plain misunderstanding.
There are analog FPGAs but they are limited. Other than that, other circuitry is just a mix of these technologies.