mentions the interface problems but doesn't go into much detail on dealing with it.
Either use diode to Vcc of correct voltage feed. And use a series resistor to limit current. But make sure to calculate the additional current load on the Vcc such that other devices use more current than the one that will spill over. An additional measure is a zenerdiode from Vcc to GND to sink excess current (Kirchhoff..).
That dedicated chip is going to have to be bidirectional on the parallel port.
The catch with this approach is that you need to tell a bidirectional variant which way signals shall flow.
Many of those people own peripherals that they once used on their original Amiga computers and might want to use them again on a modern replacement, since the FPGA clones are able to run almost all Amiga software, it would also be good if they could use some of the old Amiga third party hardware expansions, like the Miracle piano keyboard, a DCTV paint and image capture device, and other devices that connected to the Serial, or Parallel ports.
The point is that there are usually more efficient ways to accomplish what those peripherals do. Especially using I/O efficient interfaces like I2S etc. That usually also does away with any messy voltage level conversion in massive parallel arrays. Direct connection to the FPGA also imply the risk to fry the main chip.
You can do messy line interfacing and use lots of I/O to connect a sampler. Or you could use a small chip that does it all directly. Just because something is possible doesn't make it the right solution.
Edit: I have a USB to Parallel port adapter that I bought to run an old large format printer from my Windows PC.
Because USB polls no more than 1000 times /second and each transfer require a lot of setup data on top of being half duplex and hubbed. USB has some really horrible latency times (totaly unsuitable for bit-bang), throughout is way lower than one could expect, and unpredictable I/O performance.
So your USB-to-Parallel port adapter is only good for printers and LED blinking. Unless you have documentation and your willing to write a new firmware for its possible reflashable MCU.
The trick is whether or not the serial port in the FPGA minimig core can hit the MIDI serial baud rate.
Baud is signaling rate, bits per cycle. The bit rate is possible either by dividing some other clock or by using a PLL (DCM). It might require a update to the FPGA binary (core) however.
