FPGA Replay Board

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@mikej, Is there coding space in the ARM and time slices left over to make use of its built in A/D ..?
(I guess it might be hard to save to SD-card if it's too busy sampling, otoh there's RAM)

When do you estimate boards will be available for buy?

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The core of MikeJ offering is the FPGA Arcade and perhaps in the feature 060-addon. To do special one off nonstandard offerings is likely to cost more.
(as I understand it)

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FPGA Arcade with 128 MB RAM and 120 MHz CPU?

Not what I recall.

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"We can't be threesome in this marriage, you will have to end your relationship with this miss FP.GA!"

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BitcoinFPGA uses LX150-3FGG484C  (overview / datasheet) at 100 MHz which can use DCM internally to get 375 MHz (ds-page 59). It performs at 400 MH/s at an unknown frequency. And has an equalient number of logic cells of 147 443.

FPGA Arcade uses XC3S1600E-FG320-4 at 27 MHz which can be up clocked internally to at least 180 MHz via DCM or 311 MHz if the chip is a stepping 1 (page 140).  And has equalient number of logic cells of 33 192 (page 2).
(schematic page8 CDCE906 HC49-27.000)

So given the larger matrix and higher clock speed the LX150-3 would be capable to (147443/33192)*(375/180) = 9.3 times the number crunching capacity. However the LX150-3 based firmware (src) is limited to 186 MHz thus max (147443/33192)*(186/180) = 4.6 times the performance.

The board in question using LX150-3 does however employ two FPGA chips but this won't change the per chip performance.

So expect no more than 43 MH/s on FPGA Arcade. Perhaps someone can translate that into USD/s ..?

@MikeJ, Question, is the FPGA-chip used a stepping 0 or stepping 1 version ..?

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I did some calculus using the defaults on Difficulty and Bitcoins per block and it would take 4.9 years to break even economicly for the FPGA Arcade

Perhaps it's better to make other use of the FPGA Arcade..

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With a FPGA Arcade cost of 283 USD and a profit of  0.22 USD/day it would take 3.5 years to break even. It would be more profitable to put the money in state bonds

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English site version plz?

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or just get a job :/

Better to buy money

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The designer is recharging the mental batteries in order to be a more productive citizen at other times

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Bewerage meditation #80056454

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What is the cycle time on the wires to the DRAM chip? Took a look at the clock generator. And it's only 27 MHz, which should mean that EMI issues are few. Compared to any standard DVI-VGA-LVDS TFT controller board which seems to be full of series and parallell impedance corrections using passive components (DVI seems transistor boosted however).

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I meant the physical kind of EMI such that the signals reach their destination in "good shape" at all. The EMC regulation is more like a letter of indulgence payed to the emperor.

The reason for asking is that I had a look at the more powerful A/D converters available. The catch is that they demand a solid signal integrity on the PCB and anything more than dual layer co$t..

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Is it still a 64 MByte DDRx16 memory ? (so the drawing says)

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How few layers would you think could make a functional FPGA Arcade? I wonder how far one could push signals (MHz-wise) on a 2-layer board. Otoh, it's the dV/dt that is the catch not the cycle time per se.

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Asfair, the reason for the delay is that the boards need to be checked and shipped. The motivation is not profit per se. I think the mailed requests shows quite clearly how large the interest is.