FPGA Replay Board

[freqmax]

Otoh, the authorities usually require one to test before sales not while selling

[freqmax]

Maybe a plastic cover version could be made on-the-cheap?

[freqmax]

PowerPC on FPGA within grasp then finally?

@Fats, tried raw S-ATA with the board ..?

[freqmax]

@mikej, How many Hz and CPU type for that box?

Guess for larger FPGA:s compartemilisation is the feature. Lest synthesisation is going to take lots of time..

[freqmax]

That's slow for the developtment loop. Edit-compile-test-repeat..
But the time from HDL to binary needs CPU and frequency to be of a comparative nature.

[freqmax]

@Fats, see if it will work anyway? perhaps it works inoffcially

Guess it lacks "rocketport" and interleaving hack won't work?

[freqmax]

Out of curiosity how do you test the boards?

[freqmax]

I think it's doable.

It's when you need cosinustransform in FPGA that things get slightly more complicated..

[freqmax]

http://en.wikipedia.org/wiki/Discrete_cosine_transform

[freqmax]

You have approximately 81,17 ns to process each pixel which at least will involve one trigonometric function
(equal to 12 MHz)

[freqmax]

The only limitation is that someone has to write the core code & drivers to support the particular screen modes we wish to display - and the FPGA needs enough spare capacity to output the mode we're looking to support.  Yacubed estimated the Replay could support modes upto 1,280 x 1,024 - but I am guessing that's in full 24-bit mode, and that higher resolutions would be possible with less colours.

The hard limitations are:
 * Primarily memory bandwidth, (screen size) * (color depth) * (updates) = (memfreq) * (bits)
 * Memory size limits maximum resolution
 * Memory access can be lessen by using HAM-style mode. Like HAM24 etc..
 * I/O transition rate (333 Mbps/lane?) on the FPGA and number of bits wired to the video transceiver chip

Things like DDR on the memory access doubles number of bits per clock. While CPU accesses uses up some..

[freqmax]

I agree with @amigadave.

[freqmax]

I think this project is one of the most useful ever for the Amiga community. The core should guarantee that we won't run out of hardware ever..

[freqmax]

Once you have the FPGA board one can always write ones own RTG without contributions of others.

[freqmax]

With VHDL/Verilog knowledge and synthesis software on nearest PC you can make your own cores too..

[freqmax]

If you do a follow up will it be the same layout or is slight component optimization a possibility?