On the feasibility of PPC for Minimig/Fpgaarcade etc.

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I got a bit curious if it's possible to implement PPC in FPGA..

The simplest PowerPC processor Power1 uses 2,04 million transistors for logic, and 4,86 million for memory. The key is the logic gates.

Given that MC68000 has 40 000 transistors. And MC68020 uses   190 000 transistors.

The Spartan-3E 1200 used has 19 512 logic cells of which the MC68000 implementation uses 20 %. Which translates into 3902 logic cells. Which should mean that 199 022 logic cells are required. So a Virtex-5 chip like XC6VLX240T should be able to handle the task.

Maximum logic cells:
Spartan-3 33 192 logic cells.
Spartan-6 147 443 logic cells.
Virtex-6 566 784 logic cells (XC6VHX565T).
Virtex-7 2000 000 logic cells (not released yet!).

So the XC6VLX240T will likely make it possible to implement a PPC accelerator
The catch is that the free version of the programming software ISE likely won't support it. Otoh one can combine multiple chips.

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The thing about HDL-code is that once you have it, the supply is secured. Speed might suffer but you can run things. And as time progresses FPGA gets faster and cheaper while chips might be EOL'd. Though currently FPGA implementation would not be cost effective.

How is compatibility between classic PPC accelerators and currently manufacturered PPC chips?
(I recall the only available m68k has an incompatible instruction "MOVE sr,")

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The m68k in Minimig has an incompatible instruction. The question is if the same kind of issue exist between current PPC chips, and the ones used in classic accelerators.

Guess my interest in PPC on FPGA came from the issue of availability of PPC-accelerators.

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billt, Minimig uses a physical m68k chip. With a softcore you can correct anything at will.

Minimig has some constraints regarding volts, physcal package etc.. so it's slightly picky about what chip can be used asfair.

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@Iggy, The point is to be compatible with the classic accelerators. Few them ever came near any 1000 MHz ranges