MiniMig with AGA

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Chaoslord, I think he simple used DAC in the general sense, not in "a DAC" sense. And DMA only transfers, doesn't process. But the FPGA could be configured to do something in "hardware".

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If the memory transfer capacity is up to it. And vertical scan is a multiple of 25 Hz. Ie let minimig write to a display area #0 ,let the monitor read #1. Then swap when vertical sync:s occour at the same time.

Don't forget that the same memory transfer capacity is needed for feeding instructions to the cpu, samples to paula, floppy transfers, harddisc dma etc.. as well.

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Proberbly only one: m68k/32 + AGA

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In any case, "missing" cores can be designed at will.. Like 386SX, CGA and Beep in stereo!

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I hope the effort is concentrated on getting the boards free of bugs out the door

Core:s, especially 8-bit ones shouldn't even be a challenge.

Maybe the visual6502 projekt takes a look at the m68k die. It certainly could be nice to have decoded.

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To run the majority of the software. The most popular hardware platforms ought to be targeted (A500 and A1200 is my guess).

As for the CPU, maybe something else in the design could be boosted to improve performance.

And FPGA:s don't run any software. Their gates are configured after reset to interact in a specific manner. And imperative languages C++ etc.. translated to VHDL will be a serious compromise.

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The question is for whom the platform is dead for

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One can still make AGA with 12-bit suxxy D/A. The difference is slightly worse picture.

The real show stopper is the number of configurable gates (400k vs 1200k).

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It's important that the D/A is able to change the RGB color channels faster than the next pixel needs to show up. Other than that the difference is in the dithering levels available and S/N ratio.

A resistor D/A ought to have no problem with response time, but have worse S/N ratio than a chip D/A.

Btw, I heard some weird people think that it's possible to implement a whole Amiga in a little fpga chip. How ridiculus

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There's another catch there.. the tool to use it cost like 3000 USD/year.

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Is there any performance optimimum like for the instruction cache where 16-bytes gives a significant boost, but 256-bytes only gives 7% more performance increase. The idea with data cache seems a full success.

Maybe prefetch could be useful ? , because every RAM-fetch from memory require a significant setup time. So reading a few extra bytes in advance might be benefitial?

How is compatability? any software that screws up on this m68k/32 + AGA combination? There's both instruction compatibility and cycle compatibility for tight software loops?

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Just increasing the frequency is likely not as efficient as optimizing the data flows in the m68k/32 soft-core.

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I hope the boards arrive

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What's the status on the tests so far?