MiniMig with AGA

[freqmax]

At least Jens has his own A-Clone in, so his interest may be affected

The FpgaArcade board is not ready yet anyway. Like Minimig were at its release.

[freqmax]

Soldering-iron-hell?

Cookies in the oven..
http://circuitbox.net/electronics/reflow/

[freqmax]

The current gate setup will provide a 32-bit 68000 and AGA. So souped up A500. But if you look into the details, you get ~50 MB ramdisc. And most importantly it's possible to take the programmer software (Xilinx ISE) and make it 68020 + 32-bit AGA without any hardware changes.

[freqmax]

@Greg.0, where is the assembly video of fpgaarcade?

As for cores I only know of 32-bit address 68000 and AGA with 16-bit interface to CPU. My guess is 68020 or better and full 32-bit AGA might be a first "next project". Then there are all those nonimplemented chipsets to clone.

[freqmax]

@mikej, "many 68020 enhancements" enough to make it run 020 code without hickups?

Deep pipelenes, giant cache etc.. has to be a later problem
Btw, one could possible use the onboard DRAM as L1/L2 cache as the speeds are enough I suspect.

[freqmax]

Does all versions of AmigaOS 3.x run on 68000 or is a more capable cpu required?

[freqmax]

So I guess the litmustest of the softcore cpu is if it can run AmigaOS 3.9..

[freqmax]

Use a generic FPGA development board. Then it's possible show the AGA features at least?

And there's one home too asfair

[freqmax]

Maybe some people should upgrade their wife?
(just in time for the fpgaarcade board )

[freqmax]

It might be a good idea to clearify what memory modules that are suitable for the board. And maybe the softcore needs to take into account different sizes and data widths in memory modules.

[freqmax]

Rather a Picasso96 re-implementation.. as drivers are likely to already exist.

However I suspect the softcore CPU, and other basic functions need more work before other stuff can be dealt with efficiently.

[freqmax]

I think he meant if the Replay Audio implementation can record (sample) as well. Ofcourse it would require an physical ADC. A stopgap fix could be to (mis)use an LVTTL input for 1-bit sampling.

[freqmax]

I think I got temporarly confused with the Action Replay.. didn't recall any audio capabilty there..

Looking at the schematics I can see 5 possible solutions:
 (0) Resistor + Zener protect a single LVDS configured pin. Misused for 1-bit clipped sampling.
 (1) Connect an ordinary I2S ADC (possible integrated ADC/DAC) to free FPGA pins.
 (2) Use the ARM controller AT91SAM7S256-AU-001 "ADC..BUS[3:0]" which is connected to the AD4-7 multiplexed ADC inputs capable of 583 ksps. Provided there's time and codespace for this ..?
 (3) Connect the ARM USB port to a PC which is used for input.
 (4) Use some I/O on the FPGA as USB port, and connect an ordinary USB-audio device.

Is there any BOM (parts list), netlist (connection dump), gerber (layout) files available?

Thx for the link btw.

[freqmax]

Darrin, When did you write that joke?

[freqmax]

Chaoslord, I think he simple used DAC in the general sense, not in "a DAC" sense. And DMA only transfers, doesn't process. But the FPGA could be configured to do something in "hardware".

[freqmax]

If the memory transfer capacity is up to it. And vertical scan is a multiple of 25 Hz. Ie let minimig write to a display area #0 ,let the monitor read #1. Then swap when vertical sync:s occour at the same time.

Don't forget that the same memory transfer capacity is needed for feeding instructions to the cpu, samples to paula, floppy transfers, harddisc dma etc.. as well.