let's dream about the mini-minimig for a bit...

[freqmax]

OR one uses an existing development board and make an external board with all the specifics like flashholder, serial, vga etc..

BGA->SMD can be accomplished by making a board using some chinese manufacturers that does assembly.

[freqmax]

And Altera tools are M$-win32 only, unless you will sell your first born..

You could have a look at Actel FPGA.

[freqmax]

alexh:
How is Actel tools (libero?) in regards to complex statements?

One could also skip the onboard MCU and replace it with another XC3S500E FPGA + eeprom. That way fpga0 can boot from eeprom, and load fpga1 with flashmemory files. And then fpga1 can reset and load fpga0 with next set of files from flashmemory.

That way we get larger FPGA grid, and rid of one chip. Possible the m68k can be softcore aswell this way.

Btw..
"Synopsys and Microsoft Work Together to Improve Electronic Design Productivity" (abandon all hope )
http://www.ng2000.com/fw.php?tp=electronic-design

[freqmax]

An fpga-fpga internal expansion bus serialisation of 8 MHz, 16 bit data, 24 bit address gives a 3072 Mbps datarate. The XC3S500E manages 500 Mbps LVDS. So it doesn't need that many I/O ports.
And there's proberbly room for optimisations.

And yes dual fpga will consume I/O, but will also gain a lot more I/O than lost.

You can load all FPGAs from a single eeprom but the catch is that changing core will be a pain for non developers. That's why my preference for an flashmemory load.

Using MS-win kills the possibility for efficient remote console. Requires local harddisc. And gives the headache of virus etc..

[freqmax]

I defenitly agree on JTAG for development. Still the MCU function is mostly auxillary support so it should be kept at a low cost.
Also in a dual FPGA solution one could implement a flashmemory loader. And this could perform more or less at the very limit of physical components unlike any CPU.