@TobiFlex:
If you make a daughterboard with a m68k cpu. You could compare the timing with the HDL "software" cpu.
@motorollin:
It's someone doing what I thought about from the beginning. Implement Minimig with a standard FPGA developer board. That will eliminate the whole manufacturing deal.
A DE-2 board is a FPGA developer board from Altera. Which doesn't provide any Linux version of their Place & Route software as Xilinx & Actel does.
CPU and PIC can be implemented with a HDL computer language. Eliminating the need for actual physical hardware.
http://users.ece.gatech.edu/~hamblen/DE2/http://www.altera.com/education/univ/materials/boards/unv-dev-edu-boards.htmlCost: 495 USD
http://www.xess.com/prod035.php3Xilinx Spartan-3 XC3S1000 FPGA with Linux Place & Route software for free.
Cost: 199 USD
