Any pipelined dram may actually waste a lot of (dram) clock cycles as the Amiga doesn't really expect such functionality.
So a SDRAM would then receive a read command, wait1, wait2, get data and continue (or something similar).
DDR1 in essence just seems to be about different pipeline depth and voltage.
DDR2 and DDR3 use voltage levels that may be incompatible with the FPGA. At least there's currently no onboard supply to drive them. So EDO, SDRAM, DDR1 seems to be the choice of DRAM in that order.
Sidetrack: Seems SDRAM is tested with 50 pF bus load and each input is max 3,8 pF. So it should be possible to drive an array of 12 SDRAMs with one bus to accomplish a large ramdisc.
@Belial6:
Considering that most pre DDR2 dram is dirt cheap these days. I think the rational choice is to go for the simplest dram to implement.