Assembled Minimig v1.1, larger FPGA (BGA-package)

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@ThomasML:
I think you have to measure some existing Nano-ITX board :-)
(when via.com documentation is so nonexistant)

There are infact two "standard" layouts for the serial-ports (DE9).

Maybe we could arrange the RAM_xx signals in order for the v1.1 board aswell?

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@ThomasML:
I don't suggest making two versions. Just that you pay attention to which PinHead<->DE9 wiring scheme you will use.

As for the RAM_xx signals, just look at the current wiring:
http://www.opencircuits.com/Minimig_Board_v1.0_FPGA_connections
I think that if the signals are A0, A1, A2, A3 etc.. routing will be much easier and electrically sound.

If you go for the BGA route. I suggest you have the pcb board DRC checked at fab. And the FPGA-BGA assembled aswell at fab. However the rest people could do by themselfes.

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ThomasML wrote:
You're thinking about where the RAM-signals physically connects to the FPGA-package?

Yes.
Less vias => cleaner design => less emi etc..
And easier to track wires if the need arise.

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@Hans_:
Reflow oven:
* http://dlharmon.com/solder/smd.html
* http://www.seattlerobotics.org/encoder/200006/oven_art.htm
* http://www.elektor.com/magazines/2006/january/smd-reflow-soldering-oven.58007.lynkx  
* http://openhardware.net/Misc_Stuff/ToasterSMD/

Why is 68020+ needed for 24bit RGB?, dram speed have improved speed since Amiga
days, if that's the bottleneck.

Also many monitors have a hard time to make use of 24bit over analog transmission afaik. DVI or HDMI would proberbly be more suited for such high colour dynamic.

@Belial6:
How should the FPGAs cooperate?
Better to have one large FPGA. Only needs a rerun of Webpack P&R anyway. If the m68k is included in the source code anyway. Or to add/remove extra i/o capabilities.

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@Hans_:
Maybe I should ask like this, is it due memory bus speed or some other issue that a 32-bit bus is needed?

@Belial6:
Enterpoint have an assembled FPGA+32M SDram on a PGA socket header. This would allow FPGA upgrade at will. (cost 110E)

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@Hans_:
The memory bandwidth of Minimig is artificially throttled (according to Dennis). So it should be possible to use the full bandwidth of the ram to feed the AGA graphics.

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While doing BGA, a switch to DRAM would also make ram cheaper and larger.

With DRAM use + HDL cpu an ordinary pre-assembled 200 USD board can be used..

@JimS:
Putting the MCU (pic18) inside the FPGA poses an interesting chicken-and-egg problem. It will make upgrading the FPGA flash  more cumbersome. And soldered EEPROMs have a limited number of write cycles.
The EEPROM loads the FPGA. And the FPGA can then read the flashcard. But it can't reload itself.

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Yes, one could use pre-assembled ready to use developer boards. The only major obstacles is the physical CPU & Static-RAM.

VGA, Keyboard, means to load software, user i/o etc.. Is already there. I found XC3S1200 for 300 USD at digilentinc and XC3S1000 for 200 USD at xess.

This was my initial idea of an A500 implementation in FPGA. No need for special purpose boards.

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@ThomasML:
They may be large and contain stuff you don't need. But they are working out-of-the-box for those that lack soldering skills. But have programming skills.
I think a custom board is excellent, but one doesn't have to require that everyone must have one to even get started.

I suggest we move to Dynamic RAM and make the HDL code compatible with the soft m68k code with high priority (Bonus is at least 32M ram!).

@Fantoma:
Darnaw1 have onboard 16 MByte DRAM, CPU can be simulated with soft m68k core and MCU (pic18) can be coded as HDL. Though some upgrade issues may arise.

@all:
Having all the critical stuff in one premade board eliminates many EMI issues aswell.

The Webpack have builtin DDR controller and opencores.org should have support for anything older. Then adding 68k core. One will have to initially put in checks and debug the code to make it start I presume.

It's also possible to use some of the blockram in Xilinx FPGA to debug the m68k core first. And then turn to debugging Dynamic ram. The distributed ram +
blockram in XC3S1600E is 109 kByte. This would allow using the parts of kickstart as test code. And then go ahead with Dynamic RAM support on a plain developer board.

Also keep in mind that Xilinx Webpack supports upto XC3S1500 and XC3S1600E. After that you have to pay for the P&R tool.

The real bottom line with this is that we will get many more developers on Minimig. So that other issues will be resolved faster. So any coding towards DRAM + soft CPU will help other issues implicitly.

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Regarding that XESS XSA-3S1000. Maybe the CPLD could replace the pic?, and software loaded via the DB25 parallell port?

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There's one possible project with a large BGA FPGA. Adding an m68k cpu. And then construct HDL code that will compare the signals of a real cpu and a HDL version.
That would allow development and improvement of such HDL m68k cpu.