Xilinx have SDRAM application docs, so no big problem on the hardware side. One DCM will be occupied however. And a feedback line to the clock input of the SDRAM is needed. Maybe, maybe it can make do with a fake DCM clock from the MCLK or so.
I think the big obstacle is the pipeline architecture of the DRAM. Meaning the Minimig would request a memory access and get the answer ~3 memory clocks later (depend on Cas latency). Meaning the memory might have to be clocked at current memory speed x3.
PCB wire impedance, signal skew, rise time, reflection, decoupling, power supply ripple etc.. all come into play for this.
