Minimig PCB run - interest thread

[freqmax]

I have noticed that digikey.com have started to stock the XC3S400-4PQG208C at 25.45 USD for one off:
http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=122-1519-ND

They didn't before. So it was a real pain in the ass to get those chips at reasonable ease and price.

[freqmax]

The toner-transfer method: http://max8888.orcon.net.nz/pcbs.htm

Might be useful for throughhole, small boards.
But this is many components, highdensity, doublesided board. I think that requires proper methods.

[freqmax]

Anyone have a list with the exact video modes currently supported by Minimig v1.0 ..?

[freqmax]

Seems their software is Libero IDE v8.0 and is supposed to work with Redhat 4.x

[freqmax]

I have rebuilt most of the schematic in gEDA
http://rapidshare.com/files/46334959/minimig070801.tar.bz2.html
http://geda.seul.org/

If someone feels to build on it.
Btw, By useing a 1Mx16 ram one can free RAM_SEL1 by using RAM_SEL0 as additional address pin. And one sram instead of two saves a lot of wiring.

@Dennis:
Why does the sram use /UB and /LB when data is 16-bit anyway?
It works as a "enable" for each 8-bit part from what I can see.

The 28MHz fat agnus clock is generated by DCM from the PAL clock?

[freqmax]

What a mess :-)
Any idea how to make the fpga translate it into plain 16bit access? Or even 32bit.. as any sdram is likely to be organised that way.
I think the catch here is partial write where one could need to first read 16-bit (or32), modify, and then write back. Meaning the ram would have the double access time in practice.

Regarding the schematic. The most needed is the .inc files for the parts. Particulary the sd-card socket seems to be a pain (an image -> .inc program would be nice). At least the supplied would do for a hacker setup by having a ll signal solder pads done. Maybe should use a digikey.com one instead?

A clarification of the various component packages used would be useful.
The LM1117MP-adj for example is likely to be SOT23 asfair, because that's the only pkg size digikey have in stock in one-off quantities.

[freqmax]

I agree SDram is cheap enough that they are a bargain path for memory upgrade. Provided that we can figure out a sdram "driver" in verilog. Loot those evil x86 pc's :-D

As for compability. It would save some headache if boards can use the same fpga configuration binary. And in the case they can't the MCU (pic18) should select the appropiate one based on board revision.

A cheap upgrade path is to have unpopulated areas where one could add chips for sdram, composite output etc..

[freqmax]

http://rapidshare.com/files/46443453/minimig.sch.html
Almost complete.

[freqmax]

Throughhole would increase cost significantly and introduce more EMI.

[freqmax]

http://rapidshare.com/files/46669345/minimig.sch.html
Minimig schematic complete, minus the joystick port.
I used 1Mx16 ram instead of 2x 512kx16.

Headphone back-emf?
* The +1.25V and +2.5V can be connected to +3.3V to save power. Due P_heat=U_drop*I.
* Howcome the many connections to the fpga isn't in numerical order?
* What is the value of C37 100uF/6.3V ?
* Why is R42 present?, it's just sitting between +1,25V and GND.
* Howcome (54,55,56) M1,M0,M2 is connected to VccAUX, doesn't it need 3.3V?
* The 'SPI_DOUT' from the fpga and SPI_DOUT from the sdcard (via 1k) can drive eachothers output, maybe this can be resolved with an or gate or such instead?
* Maybe the keyboard and mouse can share connection?, I've seen that on laptops asfair (saves i/o).
* There's no over/under potential protection for keyboard or mouse?, like video output have. Howcome?
* Maybe the rs232 output of mcu and fpga can be shared without a jumper by setting an AND-gate between. Because the default level for rs232 is "1". And thus any transmission will produce "0", and if the other maintain the rs232 "1" resting state. IT should work.

[freqmax]

amigadave wrote:
Posting a image link to a site that requires us to register is a waste for those (like me) that don't want to bother registering at that site. Can you upload the image here?

Any tip on a better site than rapdishare.com is appriciated. I  find them a bit messy. But just took what I knew at the spot when I was tired.

[freqmax]

FrenchShark wrote:
It could be possible with a 27 MHz XTAL.
See the page:
http://www.opencircuits.com/Minimig_NTSC
Here is the computation:

27,000,000 / 429 x 455 = 28,636,363 (NTSC clock, 0 ppm)
27,000,000 / 432 x 454 = 28,375,000 (PAL clock, 6 ppm)

The DCM from the Spartan 3 accepts only coefficients from 1 to 32 :-(.
The Cyclone III accepts coefficients from 1 to 512.

The NTSC clock generation can be simplified to:
27,000,000 / 33 * 35 -> would fit into 2 cascaded DCMs.
We are less lucky with the PAL clock generation:
27,000,000 / 216 * 227 -> 227 is a prime number !

Could you explain your equations a little bit more?
27/4.433619 = 6.0898331 ie divide by 6 ..?

[freqmax]

It currently allocates 512k out of 2M as kickstart memory. With writes disabled. Any change to this can be done by changing fpga configuration.

[freqmax]

I think the unfortune fact is that there are no free pins for a parallel port on the fpga.

[freqmax]

I have summarised issues that may need attention:
http://www.opencircuits.com/Minimig_Board_v1.0_documentation

[freqmax]

Page 106 of 442:
http://www.freescale.com/files/32bit/doc/ref_manual/MC68040UM.pdf?fpsp=1

A quick count gives 43 ctrl + 32 adr + 32 data = 107 i/o pins.
So there's at least 27 new pins to connect. And the current setup only have 4 free. Thus a serious reorganisation with a southbridge solution or a enterpoint/uk PGA socketed solution would be needed.

So it proberbly can be done. But not as a plugin solution to the current setup.

As for kickstart/WB I think dennis have to tell

Btw, found another assembly house: http://www.creationtech.com/printed_board_assembly.shtml