You're mistaken. If you have a "Narrow" (8 data bits per cycle) device on a bus with "Wide" (16 bits per cycle) devices and "Wide" controller(s), then the overall width of the data path is 8 bits. How are you going to cram 16 bits through only 8 wires in a single clock cycle? The answer is you can't. You can do it in two clock cycles, but not one. That effectively cuts your overall performance in half, which is what I said earlier. I know this is true. I work for a manufacturer of SCSI periphreals. I've done tests myself in the lab and in the field. Granted, there is one way to "cheat" that I know of; that is to get decent performance on a Wide bus even with a Single-Ended device attached. In order to work, the "slow" device must not reside physically between the "target" and "initiator" hosts, both of which are presumably Wide. Second, it won't work with active termination. If these two conditions are met, then yes. it is possible to get 'close' to rated throughput. This is more true with a short bus length using LVD (Low Voltage Diff) devices. This is a dirty solution, imo. And it won't work on the Amiga/Cstorm controller anyway because it requires active termination.