First Start Minimig with FPGA-CPU!!!

[TobiFlex]

Firt time starts a full FPGA-Minimig on the DE2-Board without external CPU and PIC. I use SDRAM and a CPU-IP-CORE. The CPU-Core ist software but not timing kompatible. Thats why make some Demos Problems.

Viele Grüße
TobiFlex

[TobiFlex]

I think some day i can fit the Core also into the DE1 Board.

freqmax wrote:
@TobiFlex:
If you make a daughterboard with a m68k cpu. You could compare the timing with the HDL "software" cpu.

This is my way to verfiy the software combatibility. I have developed a CPU-Validator to compare the Hard- and the Soft-CPU. But it is very difficult that the timing will match. At this moment I see no chance.

This CPU-IP-Core has nothing to do with Wolfgangs Core. There are complete different. This is my own development.

Viele Grüße
TobiFlex

[TobiFlex]

Minimig:  6261 LCs + 172060 memory bits
CPU-Core: 3805 LCs
SPIHost:  1938 LCs + 147456 memory bits
others(SDRAM+ Sound) : 300 LCs

[TobiFlex]

downix wrote:

I just finished checking this option out.  In a word, can't be done.  The EP2C35F672-C6 FPGA it utilizes only has 32,000 gates.  The MiniMig's FPGA is 400,000 and is 80% utilized.  In short, the chipset alone won't fit into the design.

You want to annoy me. Right? Check it again and figure out your error.

[TobiFlex]

alexh wrote:
It's only 4-bit aka 16 colours, you'd need 12-bit (4096) colours for OCS/ECS and 24-bit for AGA

Thats not true.
The TREX-C1 Board and and the DE1 Board from Treasic use 4-bit per Color (4096). The DE2 Board use 8-bit per Color.
The TREX-C1 Board is to small for the Minimig. The DE2 Board is to expensive for the most people but its very nice for debugging the Core.
My goal is to use the DE1 Board for the Minimig. It cost 150$. But I must rewrite the SPIhost to use exteral RAM.

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=39&No=83

[TobiFlex]

Hi Dennis,
I would like to make the source code also open source some day.
Viele Grüße
TobiFlex