I've started to re-write the Minimig core and tidy it up with Jakubs support into a VHDL version which will be easier to maintain.
Mike, keep up the good work.
I do have one concern for MiniMIG core.
MiniMig core is currently in Verilog (except for the soft 68K which is in VHDL) on these Targets:
1. MiniMig (no soft 68K)
2. MiniMig_ITX (no soft 68K)
3. C-One (soft 68K)
4. Altera DE1/DE2 (soft 68K)
5. MCC-Arcade (soft 68K)
Thus, the port of the MiniMig Core to VHDL may not be the best for the MiniMig core since the five other ports/targets are currently in Verilog and changes done to a VHDL MiniMig port will get out of Sync and be unique. This could cause support/updates to cease for the other targets.
