mikej wrote:
Peter's C64 core has already been ported and runs on my standard Spartan3e board (we have been chatting for a while). I haven't released the port on fpgaarcade as I'm waiting to include a highly accurate SID port - and it needs the DDR RAM controller which is not quite finished yet.
Mike,
Are you writing your own DDR controller or are you using the Xilinx DDR controller from the Xilinx Core generator/MIG ? I have used the Xilinx DDR controller from Core generator/MIG, and it seems to work ok on the Xilinx Spartan3e evaluation board.
I would like to try out FPGA64 on my Xilinx Spartan3e evaluation board. Please let me know when you can release/post the project & source code.
:-)
