MiniMig: One Random CRAZY Thought.

[jkonstan]

SDRAM is a move forgiving on the PCB layout than DDR.
DDR with a Xilinx FPGA will work fine; however, PCB layout rules and signal integrity analysis must be followed in order to insure a properly working memory implementation.

 :-)

[jkonstan]

freqmax wrote:
@jkonstan:
What do I have to do when it comes to pcb layout to make sure SDRAM will work?

Also what DRAM access time does the 7.09379 MHz Minimig demand? (it had four cycles or so?)
The current sdram is 70 ns. But that's maybe faster than needed.

In order to insure that the SDRAM works, the answer is complex and may be out of scope for a simple post. The proper recipe deals with a static timing analysis & Signal Integrity (PCB stack up, series termination resistors, trace lengths, trace impedances, and a Signal Integrity simulation tool such as HyperLynx from Mentor).

If you really want to know more about this, I can write up more after I finish assembling my MiniMIG1.1.

Also, this book is a good starting point/reference.

http://www.amazon.com/Handbook-Digital-Techniques-High-Speed-Design/dp/013142291X

 :-)