Assembled Minimig v1.1, larger FPGA (BGA-package)

[jkonstan]

Did you rebuild the MiniMIG Xilinx ISE Project with the new Spartan3E part/BGA package to make sure that new pin out would route (i.e. is the resulting pinout from Xilinx ISE floor planner)?

Also, please see Xilinx Spartan3/3E APP notes on BGA 4/6layer PCB and on SSO (Simultaneous switched outputs).

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?iLanguageID=1&category=Publications/FPGA+Device+Families/Spartan-3E/Application+Notes
Check Xilinx XAPP689.pdf
Check Xilinx Xapp489.pdf

 :-)

[jkonstan]

Thomas,

Please connect the MC68SEC000 Berr* pin12 to one of those  FPGA pins.

 :-)

[jkonstan]

Thomas,

Please see this Open Circuits MiniMIG link where I explain why Berr* would be a nice to add back into the design.

http://www.opencircuits.com/Minimig_68K_CPU_BERR%2A_Support

  :-)