Minimig PCB run - interest thread

[jkonstan]

arnljot wrote:

So this is what I think could help:
1) Split the project into two under one umbrella.
- Minimig Hardware
- Minimig firmware
2) The umbrella project should (third toplevel project)
- Handle feature request, bug reports and coordinate effort from "third parties"
- Organize bounties:
-- Firmware coding bounties
-- Hardware design bounties
-- Hardware manufacturing bounties (the minimig shop?)

I really like the idea of adding hardware/firmware bounties because it assigns tasks and allows for a way to try to recover some hardware development costs. It can get a little pricey building low volume prototypes.



 :-)

[jkonstan]

The issue with USB host on the present Minimig PCB would be the lack of CPU MIPs (the slow clock speed of the 68SEC000 CPU) and lack of spare FPGA I/O pins. A seperate CPU on a USB HOST controller such as the FTDI Vinculum USB HOST controller might work becasue it has a seperate CPU of its own running the USB stack although we would have to use a SPI interface to connect to it since we only have 4 spare FPGA I/O pins. The speed of a serial SPI connection from 68K/Xilinx_FPGA  would most likely limit the bandwidth/transfer rate. Data sheet has Vinculum SPI port max SPI Clock = 10Mhz => 10Mbits/sec Max SPI transfer rate (if no signal integrity issues arise). A FTDI Vinculum USB HOST controller small daughtercard that connected to MiniMIG1 Spare I/O header J9 could be built. We may have enough 68K CPU MIPS to handle this kind of implementation.  

http://www.vinculum.com/


Other soft USB option (not feasible on MiniMIG1.0):
A usb phy connected to an FPGA would require @ 7 FPGA I/O pins and an embedded Xilinx microblaze soft CPU core to run the USB Stack. The USB stack is large; thus, the microblaze CPU would need external RAM access. The RAM is tied up by the 68K and FPGA_AMIGA_Chipset. Thus, the soft USB option does not look to good for MiniMIG1.0.

http://www.fairchildsemi.com/ds/US/USB1T11A.pdf

 :-)

[jkonstan]

Spartan3 I/O is programable/flexible; however, I am not so sure that it is flexible enough to eliminate the need for an external USB HOST Physical layer. I would probably count on needing an external USB HOST physical layer such as the Fairchild part below.

http://www.fairchildsemi.com/ds/US/USB1T11A.pdf

Actually, replacing the 68SEC000 CPU with part of the Xilinx Spartan3 might be an option. I have the downloaded the VHDL source to an ATARI ST project that includes an almost finished 68K CPU. This would free up lots of FPGA pins.

I need to get my MiniMIG(s) going so that I can get some development going.

  :-)

[jkonstan]

 

TobiFlex wrote:

source to an ATARI ST project that includes an almost finished 68K CPU

This CPU Core is not finish. The Debuging must go on. Currently hangs up this CPU Core with Kickstartrom 2.04 at #$F81914.

Viele Grüße
TobiFlex

What set of Amiga hardware are you debugging the 68K VHDL CPU core with? Do you have an estimated clock rate for the 68K core in a Spartan3 FPGA ? I was going to try the 68K VHDL CPU core when I got my MiniMIG going.
Thank you for the update on it.


 :-)

[jkonstan]

TobiFlex wrote:
I have adapted the minimig Core to the DE2 Board from Terasic with a ALTERA Cyclone 2C35. With an external CPU MC68HC000 runs the Minimig perfekt. I have change the RAM Timing from SRAM to SDRAM - so i can use the on Board SDRAM Chip.

And now i use the Board to Debug Wolfgangs 68K Core.

Sounds as though you are using a stock FPGA evaluation/development board possibly with some adpater PCBs that you built.

More questions because I have a few evaluation FPGA boards as well ...
Q1) Did you build a PIC adapter PCB as Dennis had for the Spartan3 Eval board or did you use the Altera DE2 SD socket and write a bunch of code in order to replace the floppy ?
Q2) The current Verilog implementation on MiniMIG essentially runs 0 wait states with the external SRAM. Have you modified the MiniMIG Verilog core to allow for wait states so that SDRAM or DDR can be adapted ?
Q3) How do you find an affordable Altera DE2 ? Those are expensive unless you get the student discount ?


 :-)

[jkonstan]

Since I have been busy working on trying to get a couple MiniMIGs put together, I have not yet compiled Wolfgang's 68K VHDL core; thus, I was not aware of its size in terms of Xilinx CLBs.

I agree completely that the 68SEC000 is pretty cheap $7 to $11; however, I was thinking more of getting around some of the present limitations of MiniMIG1:

1. The lack of more FPGA pins (soldering hobby/home project limit of 208 pin QFP on FPGA). The new extra FPGA pins could be used for IDE, Compact FLASH, parallel interface to Vinculum VNC1L (USB host controller with a CPU core and USB stack),  etc ....

2. The 68K bus clock rate limit on a two layer PCB. A larger Xilinx FPGA (more CLBs) with a soft 68K core embedded in it could possibly clock the soft 68K faster than the external 68SEC000. This would have to be investigated by compiling Wolfgang's VHDL code and running Xilinx timing analyser on it.

   :-)

[jkonstan]

mongo wrote:
There are enough free pins on the FPGA to do IDE as it is with a few external components and Compact Flash can also be connected via the IDE port.

I agree that Spartan3E is better way to go on an update to MiniMIG.

I have implemented several IDE interface in Verilog over the years; thus, I am pretty curious. There are 4 spare FPGA spare I/O pins left in MiniMIG1. How do you intend to support/implement an IDE interface (IDE_RESET, CS0*, CS1*, INTRQ, DMREQ, DMACK, IORDY, IORD*, IOWR*, ICS16*, DASP*, DA0-DA2, DB0-DB15) which require at least 12 FPGA I/O pins and some external CBT16245 level shifters used on 68K bus ?

Also, I was not thinking of using the compact FLASH card in IDE mode (where Pin9 is pulled to ground and only good for compact flash memory cards).  My thought was to have a compact flash socket that was actually supported compact flash peripheral cards as well such as ethernet and serial port cards (i.e. Full Compact FLASH socket mode = PCMCIA with reduced number of address lines).

 :-)

[jkonstan]

Doobrey wrote:

Any idea if Freescale's 68306 would work fairly easily? ( straightaway I can see some work needed to convert IPL2:0 to the 306's separate IRQ lines).

Looks like its built in DRAM controller would make adding upto 64MB pretty easy, plus there's some programmable chip selects and IO pins for extra hackable goodness :hammer:

MC68306 could work since it is based on the 68HC000 core.
This is a nice idea (especially with the JTAG port on the MC68306); however, the MC68306 would have issues. The MC68306 DRAM controller works only with old obsolete DRAM which is no longer produced anymore. MC68306 is a 5Volt I/O part; thus, we would have to use level shifters between 5V MC68306 <=> 3.3V FPGA. Thus, there is not as much benefit in using MC68306 as we would like.

 :-)

[jkonstan]

mongo wrote:
Address and Data lines connect to the 68K via level shifters, same with the Reset line. IORD*, IOWR* CS0*, and CS1* can easily be generated completely externally, though you can reduce the number of external components if you use one output line of the FPGA as a IDE Chip Select line. IORDY has to go to the FPGA for it to generate wait states for the 68K if needed, but even that might not be totally necessary unless you plan on using a really old drive. INTRQ has to go to the FPGA, unless you want to poll the drive instead of using interrupts, but I don't recommend doing that if you don't have to.

DMARQ, DMACK, ICS16*, and DASP* aren't needed.

3 FPGA I/O pins and a few external components are all that are required.

Your description shows that you need more than the 4 programmable FPGA Spare I/O pins that are left on MiniMIG Ver1.0 J9 header in order to build the IDE interface that you described and that the MiniMIG PCB would need a new PCB layout. Of course if you add a CPLD/external logic and a bunch of level shifters to MiniMIG, a PIO mode IDE interface could be built.

PI/O IDE is ok; however, DMA can be nice when one can DMA directly into SRAM. Thus, I would not write off the need for DMAREQ and DMACK.

IORDY for IDE would be nice when some users trys to hook there old small IDE hardrives from their old Amigas onto a MiniMIG at some point.

  :-)

[jkonstan]

freqmax wrote:
The 68306 product summary only says "Available in 5V". Looking in the datasheets there's no mention of 3.3V. I still fail to see the benefits besides address space. Any DRAM is better controlled by the FPGA where it can be used both as Chip and Fast ram.

If 'TobiFlex' succeeded to use sdram. It would be interesting to find out more in order to replace the 2M Async SRAM with 32-64 MB DRAM or more.

One possible setup is to have two FPGAs and one XCF02S configuration memory.
FPGA0 bootloads configuration from eeprom. And loads data from SD/MMC to configurate FPGA1. FPGA1 loads data from SD/MMC to re-configurate FPGA0. Both bootloaders are deactivated. And normal operation is initiated.
This could allow elimination of the MCU and allow one extra FPGA for m68k vhdl/verilog core. Aswell as plenty of I/O pins to play with.

Use of the dual FPGA scheme could get us more free/open FPGA I/O pins and potentially replace the PIC. The soft 68K CPU core or an additional soft Microblaze CPU could control the SD card as well. In order to lower the cost of the Xilinx FPGAs and expensive Xilinx Configuration serial device, the use of the Spartan3E FPGA which is lower cost and can use  lower cost SPI FLASH (ATMEL, ST, and Spansion) for configuration should be considered (see App note below).

http://www.xilinx.com/bvdocs/appnotes/xapp445.pdf

Also, maybe TobiFlex will share some of his FPGA SD card (floppy replacement)development so that we do not have to re-invent it.

 :-)