Minimig PCB run - interest thread

[jkonstan]

 I am interested in two to four unpopulated boards.

 :-)

[jkonstan]

68AW512M ,an ST 512Kx16 SRAM in a 44 pin TSSOPII package, is no longer produced. We will have to substitue a Cypress (CY62157EV30LL-45ZSXI), ISSI (IS62WV51216BLL-55TI), or Renesas (HM62V16514LTTI-5) SRAM.

 :-)

[jkonstan]

All of these SRAM parts below (55nsec or faster) share a common pinout and TSSOPII footprint:

68AW512M ,an ST 512Kx16 SRAM in a 44 pin TSSOPII package

Cypress (CY62157EV30LL-45ZSXI) 512Kx16 SRAM in a 44 pin TSSOPII package

ISSI (IS62WV51216BLL-55TI) 512Kx16 SRAM in a 44 pin TSSOPII package

Renesas (HM62V16514LTTI-5) 512Kx16 SRAM in a 44 pin TSSOPII package

What could be different and may cause an issue between these SRAM parts is ground/VCC bounce since the PCB is only 2layer and lends itself to a higher inductive volatge drop Ldi/dt on the power and ground connections to the ICs. We can only tell this by testing some of these SRAM parts in an actual 2layer MiniMig PCB.


 :-)

[jkonstan]

Dennis,

For a 2layer PCB, you did a nice job on the layout and helped to keep the blank pcb very affordable.

The concern with the other brands of SRAM (Cypress (CY62157EV30LL-45ZSXI), ISSI (IS62WV51216BLL-55TI),
Renesas (HM62V16514LTTI-5) on a 2layer PCB is the differing levels of Ldi/dt drop for those vs the ST SRAMS. The different brands of SRAM will all draw different amounts of instantaneous current when the SRAM is being accessed (read or write cycle). If you have any pcbs still not fully populated and could validate one of these other brands of SRAM, it would be helpfull.


  :-)

[jkonstan]

The CY62167DV30 1Megx16 SRAM is in a TSSOP 48 pin package, and the 512Kx16 SRAMS are in a TSSOPII 44 pin package. The Cypress 1Mx16 and 512Kx16 SRAMs have different packages and differnet pinouts.

If the MiniMIG schematic and PCB layout were updated for the CY62167DV30 1Megx16 SRAM (TSSOP 48 pin package), the CY62167DV30 1Megx16 Cypress SRAM could possibly be used instead of two of the 512Kx16 SRAMS.
 
:-)

[jkonstan]

The decoupling cap next to the IC will help VCC dip/bounce; however, it will not help with ground bounce. Ground bounce is fixed by use of a low L inductance ground path connection for the IC/SRAMs (i.e. a ground plane).

 :-)

[jkonstan]

Nusim,

The MiniMIG pcb 1.0 run sounds good to me.
 
I am interested in a MiniMIG blank pcb 1.0, and I am one of those serious electronics experimenters.

Please let us know when these become available.


  :-)

[jkonstan]

Thanks for the schematic.

The UB & LB strobes on the SRAM are due to data bus addressing needed for the 68K cpu. 68K CPU has UDS* strobe for upper byte lane D15-D8 access, and 68K CPU has LDS* strobe for lower byte lane D7-D0 access. When 68K does a read, D15-D0 can be accessed as a word with 68K reading what it requires off of its Databus; however, a write access on a 68K CPU requires the byte lane be qualified. When UDS* active on a write cycle, UB* on SRAM must be active. When LDS* active on a write cycle, LB* on SRAM must be active.  

D15 ........D8,,,,,,,,,D7........D0
Byte 0= Even,,,,,,,,Byte 1= Odd   =>  (Word 0)          
/UDS ,,,,,,,,,,,,,,,,,,,/LDS    

etc ....



 :-)

[jkonstan]

I agree with Dennis to keep the 1st batch/run of MiniMIGs compatible so that the base set of Verilog HDL and 68K boot code runs on it so enhancements to these can be added on a stable hardware platform. Some kind of very limited expansion could be via the four pins of SPARE I/O FPGA expansion on MiniMIG.

For MiniMIG Gen2 (A1200 like), a 68020 (or maybe even a Freescale 683xx CPU32) would be probably be the way to proceed. With the dynamic bus sizing on the 68020, we could choose a 32bit or 16bit databus back to the FPGA where some similarity to 68000 Bus exists in 16bit 68020 bus mode. A 68020, SDRAM, IDE, compact FLASH, Amiga Clock port, and maybe USB would be good for Gen2. The issue that we are going to have is runnig out of pins on a QFP Xilinx FPGA. Gen 2 MiniMIG could really use a bigger Xilinx FPGA in a BGA package; however, this would push us into a 4 or 6 layer PCB and also require BGA rework equipment to assemble. SDRAM controller is available in Xilinx MIG/Core generator and also on www.OpenCores.com. I have in the past written Compact Flash and PIO IDE controllers in Verilog as well as designed 68020 embedded hardware. I am willing to help on a MiniMIG Gen2.

 :-)

[jkonstan]

A USB Host Controller usually connects back to a host processor on a high bandwidth bus (parallel CPU bus, PCI, clock port, etc ..) in order to be able have high bandwidth transfers. The Vinculum parallel FIFO interface mode with 8 bit bi-directional data bus and simple 4 wire handshake for data I/O and command monitor interface would work well interfaced back to the Xilinx FPGA or to the 68K bus. The issue with USB host on the present Minimig PCB would be the speed of a serial SPI connection from 68K/Xilinx_FPGA to a Vinculum USB HOST controller that would most likely limit the bandwidth/transfer rate. Data sheet has Vinculum SPI port max SPI Clock = 10Mhz => 10Mbits/sec Max SPI transfer rate; thus, a Vinculum SPI connection in any application will have a limit on the SPI tranfer rate of 10Mbits/sec or maybe lower due to possible signal integrity issues on a 2layer PCB.

Also, USB 2.0 compliant device does not have to support USB 2.0 High speed (480Mbits/sec) transfer mode. A USB 2.0 compliant device such as Vinculum only have to support "Basic-Speed" of 1.5Mbits/sec (Low speed) & 12Mbits/sec (Full Speed) while ignoring the high speed handshake from a USB 2.0 High speed (480Mbits/sec) device so that the High Speed device (480Mbits/sec) will kick back down to the old 12Mbits/sec (Full Speed) speed mode.

  :-)

[jkonstan]

I have actually had two bare MiniMIG 1.0 PCBs produced for myself based on Ver1.0 gerber files/layout, and I am gathering up the parts in order to assemble them by hand.

 :-)

[jkonstan]

DigiKey is the source for a fair portion of my parts for my MiniMIG. I may also buy some parts from Mouser Electronics & Jameco. Digikey & Ebay are options for the Xilinx Spartan3 208QFPs FPGA.
 :-)

[jkonstan]

Amigadave,

I fabbed these two blank PCBs so that I could try to help with the development/enhancement of MiniMIG. The two Ver 1.0 blank boards were fairly pricey (over $25/each without electrical test) as compared to some of the other better efforts that were already on going to produce a bunch of cheaper blank PCBs. An AROS related individual/group was going to produce a batch of the original Ver 1.0 PCBs for sale, and the original starter of this thread had the mass production covered for Ver 1.1 of this updated PCB artwork. I thought that would have everyone pretty much covered without someone else mucking up the waters.  I really do try to stay focused on the technical side of things.

 :-)

[jkonstan]

arnljot wrote:

So this is what I think could help:
1) Split the project into two under one umbrella.
- Minimig Hardware
- Minimig firmware
2) The umbrella project should (third toplevel project)
- Handle feature request, bug reports and coordinate effort from "third parties"
- Organize bounties:
-- Firmware coding bounties
-- Hardware design bounties
-- Hardware manufacturing bounties (the minimig shop?)

I really like the idea of adding hardware/firmware bounties because it assigns tasks and allows for a way to try to recover some hardware development costs. It can get a little pricey building low volume prototypes.



 :-)

[jkonstan]

The issue with USB host on the present Minimig PCB would be the lack of CPU MIPs (the slow clock speed of the 68SEC000 CPU) and lack of spare FPGA I/O pins. A seperate CPU on a USB HOST controller such as the FTDI Vinculum USB HOST controller might work becasue it has a seperate CPU of its own running the USB stack although we would have to use a SPI interface to connect to it since we only have 4 spare FPGA I/O pins. The speed of a serial SPI connection from 68K/Xilinx_FPGA  would most likely limit the bandwidth/transfer rate. Data sheet has Vinculum SPI port max SPI Clock = 10Mhz => 10Mbits/sec Max SPI transfer rate (if no signal integrity issues arise). A FTDI Vinculum USB HOST controller small daughtercard that connected to MiniMIG1 Spare I/O header J9 could be built. We may have enough 68K CPU MIPS to handle this kind of implementation.  

http://www.vinculum.com/


Other soft USB option (not feasible on MiniMIG1.0):
A usb phy connected to an FPGA would require @ 7 FPGA I/O pins and an embedded Xilinx microblaze soft CPU core to run the USB Stack. The USB stack is large; thus, the microblaze CPU would need external RAM access. The RAM is tied up by the 68K and FPGA_AMIGA_Chipset. Thus, the soft USB option does not look to good for MiniMIG1.0.

http://www.fairchildsemi.com/ds/US/USB1T11A.pdf

 :-)