in case you are interested to test new fpga accelerators for a600/a500

[mikej]

I wish the team well, even though Gunnar has for some unknown reason got irritated with the Fpgaarcade team.

I've been pushing back a few fixes for the T68 soft core we currently use. There are potentially a few issues remaining with the 68020 mode,which are problematic to find.
I've developed a daughterboard with a real 68020 (and the rest of the AGA chip set) so I can run the soft cores against the originals and hopefully nail any functional / timing differences.

I am making some progress getting a public SVN mirror up, I expect this to be done in the next couple of weeks which will hopefully pacify some of the more zealous open source people in the community.

Anyhow, for me, 100% functional compatibility is the number one priority, followed by cycle accurate timing in 68000 mode. Then, maximum performance in 68020 mode.

I now have a functional model and microcode dump of a real 68K which is helping design a very lightweight new (open source) core.

One comment I will make (and please don't take offence Phoenix team) is I find it very unlikely you will be able to produce an ASIC. For my day job I design 28nm devices, and the mask costs are high. The cost of respins is high. I'm very open to helping out if you think it is doable.

Anyhow its a small community, lets all work and play together peacefully.
Cheers,

Mike
http://www.fpgaarcade.com

[mikej]

Hi Mike,

The issue is very easy to explain.
People told us that you "warned/informed" them that  my SAGA chipset
would be based on a copy of a patched Minimig chipset.

Thanks for the response. News to me, I have no idea what you are up to (it being closed source) and hence how could I comment? I think there is some miss-communication here with a 3rd party perhaps.

I have however received "demands" for my code (people assume it is minimig derived) however for use with a Phoenix core, which I politely turned down as it's not released yet.

It is now working pretty much, and will be released.
Best,
Mike

[mikej]

Ah yes, I talked to Till about this while I was giving him some T68 updates.

It was a bit of a case of Chinese whispers to be honest, and Till has already apologized to me for any miss-understanding. It would appear Gunnar was a little overly sensitive.

I am continuously surprised at the politics, it all seems a bit unnecessary to be honest.
/Mike

[mikej]

so since everybody is a bit sensitive about their projects and surprised about the politics, can this be considered settled in order to start over in mutual respect?

There was never any disrespect from my side.

Absolutely, with communication, tolerance and respect from all sides, this small community would certainly be a happier place.

Mike.

[mikej]

Mike, do you see a need for and would you support a standard's committee?

Matthey,

I totally agree that without some form of standardisation the community will fracture.

From a CPU perspective, I see absolutely no point adding or changing any instructions - I'm focussing on functional and timing accuracy for the 68000, then performance for the 68020+.

Personally, if you are going to mess around with the architecture sufficiently to force a compiler modification, you might as well recompile to something else entirely. ARM or MIPs spring to mind.

For the chipset I have already made a few obvious improvements, such as extending all the DMA address register widths. There is not particularly controversial as there is space to do this in the memory map.

I don't expect software to use it, but if this sort of enhancement could be documented and agreed on, it becomes a possibility.

So yes, happy to be involved.

/Mike

[mikej]

The T68 softcore is close to 68020 compatibility (and I'm still fixing it). It certainly boots up kick 3.0 on an AGA 1200 core no problem.
MikeJ