MiniMig with AGA

[mikej]

My thoughts exactly.
/MikeJ

[mikej]

I haven't actually seen the new code yet, but from my Atari work it is easy to do this sort of thing.

Plane mode is least efficient from a DRAM point of view. What I did with the ST is to burst read a chunk from each plane from the DRAM and hold it in a local RAM cache. I can then combine each plane how I like. The DRAM access is very efficient as it is reading 8 word burst access per plane. I wrote it to support 32 planes, and they all share one RAM block.

For chunky modes you just cut up the data as it arrives into suitable size, um, chunks.

It has to work in legacy mode of course as well, these new modes are no use unless we write a driver to support them.
/Mike

[mikej]

I didn't even know the ST had planar graphics modes. I thought it supported 16, 4 or 2 colours on screen, in a chunky format.

However planar graphics in conjunction with a fast (potentially full scanline, but actually only needs to be the optimal size of a DRAM burst access per plane) cache as you describe isn't so bad for outputting the graphics to a monitor.

In the original machine the planes are interleaved in 16 bit words, so in 4 plane mode you get
     
 plane 0 |plane 1 |plane 2 |plane 3 |plane 0 | etc

but I wanted to expand this. Just messing around to play with the memory controller to be honest.
/MikeJ

[mikej]

@MikeJ

Will the cores be released as opensource when they are ready?

In general yes, I am a very keen on everything being open.

If there are any IP issues (I can only think of two, one being part of the ST chip set and the other part of my memory controller) I'll release that sub-module as obfuscated (scrambled) VHDL. In this way you can still recompile the chip and add new features to 99% of the code.

I intend all the code to be fully open from day one if possible, so I hope this will not be necessary.

The ARM code will also be available as are the schematics and a developer wrapper file for the FPGA which drives the various interfaces and has a standard interface to the different cores.

Best,
Mike

[mikej]

Very nice!
I'll be releasing the mechanicals shortly, so you can see if the board will fit.
/Mike

[mikej]

I just tried one of the RevA boards in a ATX case to check the hole alignement and the holes are in the right place, and the IO lines up.

So, should be good for mini-ITX box.
/Mike

[mikej]

When I have the board in my hand I'll see if I can find a metal vendor who can stamp them out. I am not sure how accurate my CAD models of the connectors are. If I can just send one to a chinese vendor and say "may me one that fits that" it would be great.

The PCBs are delayed slightly as some components are on long lead time. The bare boards are in China and I am not at the moment, so we need to get reunited

I'll let you know as soon as I know.
/Mike

[mikej]

Still waiting for some components...
/Mike

[mikej]

I don't know why but some parts are on lead times of 2 months!
I'm trying to get enough samples to at least build the first few for testing while I wait for the rest of the bits.
I'll keep you posted.
/Mike

[mikej]

A couple of semiconductors, mainly the DAC.I've got a few samples now.

I've released the schematic and board mechanicals

http://www.fpgaarcade.com

/MikeJ

[mikej]

In that case I suggest Loriano makes a mini A1000 case. I'd like the ability to slide a Solidtek ASK-3100SP mini keyboard under the case. I'm lucky enough to have a PS2 one.

That would be fantastic, thanks.

I need to update the dimension drawing. I'll remove the connector details and do a second drawing with the heights. I need this to make the ATX panel thingy.

/Mike

[mikej]

The main card has the following :

P1  2 pin RS232 select jumber for debug (ARM or FPGA)
P2  2 pin 5V external power input
P3  32 pin IO cable expansion 1
P4  9 pinD RS232
P5  Molex 12V/5V external power input
P6  2.1mm 5V power input for wall adapter
P7  32 pin IO cable expansion 2
P8  main SAMTEC board stacking connector. Lots of IO
P9  3 pin ARM debug serial connector
P10 2 pin ARM ERASE
P11 2 pin ARM TST
P12 micro USB (for updating ARM firmware)
P13 6 pin  FPGA JTAG debug
P14 5 pin USB header (parallel with P12)
P15 sub SAMTEC board stacking connector. Video+Audio+Joysticks
P16 SD card
P17 2 pin external ARM reset input
P18 2 x 9pinD enhanced joystick inputs
P19 2 pin soft reset input (parallel with S2 push button)
P20 SVHS / composite video output
P21 2 x 6pin PS2 inputs (mouse / keyboard)
P22 DVI output (HDMI + analogue video for SCART/VGA)
P23 3.5mm stereo audio output

There is also a patch area to the left of P3 which has some test points for wiring up extra IO.

I have a floppy connector on one of my expansion patch boards - you can see pictures of this board on the FPGAArcade website if you scroll down a bit.

I might add one to the release expansion board, it's easy to do and might be useful.
/Mike

[mikej]

The bare PCBs will be finished this week, I have been told....
/Mike

[mikej]

Update:
The PCB house has made a mistake with the impedance control in the board. They found this during testing and have almost finished re-making the first 60 boards.

It's not going to delay us (any more) as we are still missing the DACs....

Firmware is progressing. I am working on correcting some compatibility issues with the soft 68K core at the moment.
/Mike

[mikej]

The boards are 100% electrically tested for continuity.

This PCB has controlled impedance on all layers, so when they make it they also do a test strip. The spacing is calculated by me and modified where necessary by the PCB people to get my desired impedance. After production they test it to make sure the boards are in spec. Sadly in this case they used the wrong layer stackup, so the boards were slightly out.

It happens, they have fixed it. No problem.
/Mike

[mikej]

Sheesh, people.  This system has been on the boards for a couple years now.  Go to the source if you really want to know more about this board.

http://www.fpgaarcade.com

Thanks Ferrellsl.

I've attached a pic of the new PCB. I haven't actually got it in my hands yet though.

Basically the board was designed as a general platform for my retro projects, arcade games and computer systems.  The Amiga core is ported to the board and I will maintain it. Jakub is working on AGA enhancements and I'm working on testing the soft CPU cores.
/Mike