TG68 - The Open Source Minimig CPU into the FPGA

[Dennis]

Excellent news!!

This opens up some whole new possibilities...
(pondering about Minimig rev2.0  :-D )

[Dennis]

I did a quick compile with webpack 6.3.03i:

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4

 Number of Slices:                    2627  out of   3584    73%  
 Number of Slice Flip Flops:          1052  out of   7168    14%  
 Number of 4 input LUTs:              4841  out of   7168    67%  
 Number of bonded IOBs:                 74  out of    141    52%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.


Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 39.906ns (Maximum Frequency: 25.059MHz)
   Minimum input arrival time before clock: 16.900ns
   Maximum output required time after clock: 16.576ns
   Maximum combinational path delay: No path found

I need a bigger FPGA  :lol:

[Dennis]

I'm also on the bridge, Captain.

Aye, aye!

[Dennis]

The cores for Tobiflex' ports to the Terasic DE1 and DE2 boards are now available for download at my
website

Have fun  :-D