A500/A600 Accelerator

[hppacito]

Hallo everyone,

This post is to inform you of the status of the project.

The though part was to get the components, being Flash chips and SRAMs the most difficult.
SRAMs should arrive in few days, and Flash should arrive the first week of January.

With these components, I can now complete the design of the board, because the packagings you know, are varied.

I even got, a couple of weeks ago, the ethernet chip RTL8019AS, that is available for end unsers in Germany.

Technically, an hybrid accelerator A500/A600 is possible in the same board, with the same circuit. Maybe is not physically possible, but that is something else.

I got enough components for a small run of 10 boards, including 2 protos. I will build the protos, and I hope someone (besides me) will like to test them also.

That testing time, will be used to write drivers for the IDE controllers (2) and for the rtl8019AS (gladly, there is open source drivers available).

Both IDE and Eth will have interrupt capability.
Memory will use autoconfig, and will be separated in two areas, a 4MB area (@ 0x20 0000), and a 1.5MB area (@ 0xC0 0000).
In the case of an A500, the 1.5MB area should be remapped to 0x60 0000 to have a 6MB continuous block, it is actually a 2MB block.

The original kick rom, should be copied to flash, by means of a small utility. This same flash, can hold more than one kickstart.

ps: If anyone know how to program a driver, that can be copied in ROM and is initializated by the kickstart, let me know. That is going to be useful for the IDE controller.
(ps: anyone with good soft knowledge may be wants to help with all this ?, send me a message)

ps2: As I said earlier, the price should be around 90 Euro, without shipping. No shipping if you show up at my door, may be even with a free beer ;-)

Well, as soon as I have more info, I'll post it here.


Greetings

[hppacito]

@ Doppie1200:

A PLCC68 socket will be provided to plug over the 68k, don't worry, but both sockets will not fit at the same time, though.

[hppacito]

Hallo,

The plan is to clock it at 16 MHz. Higher clocks can be achieved, but I don't know how much those 68EC020 can be pushed. They are -16 parts, means were meant for 16.67 MHz, a couple more MHz can be squizzed, but another limiting factor will be the flash rom. 70 ns flash should work even at 20MHz... but all that should be tested.
Remember that memory will be accessed in 3 cycles (except chip of course), so that should achieve maximum throughput... and so performance.

I'm a bit late with this due to my phd demanding some work from my part ;-) but hope to get again on track very soon.

The A500 version uses the DIP connector, so should be pluggable in an A2000, but I don't have one to test... (any volunteers ;-))

regards, and thanks all for the great support !, I hope I can deliver something soon

[hppacito]

Until I was arount 18, I was sure I'll study Electronics. But that very year I changed for chemistry. I think gives more of "how the things work" than EE.... time will tell ;-)

[hppacito]

Ja,

I'm still working on it to fit all components in such small board !, and down to 2 layers.

Thanks for the support !