Poll, new accelerator for A500/A600.

[hppacito]

Hallo everyone,

As I'm in the process of developing a new accelerator for A500s and A600, in the performance range 10 to 15 MIPS, based on a ColdFire chip.

The prototypes will be quite light in features (ColdFire, ram, flash, 68k connector, maybe ide port). But I'd like to make something better suited for day-today use.

The idea is:

SDRAM soldered to the MB (because DIMMs are 64 bits, so 1/2 would be wasted) 16/32/64/128 MB (decide the best number)
IDE port, 2 devices with DMA support.
CF port.
10/100 Ethernet port

any ideas ?

[hppacito]

The prototype will be done with a MFC5206E with 4 or 8 MB SRAM.
The following will be with a MFC5271, MFC5208 or MFC5407. I'll decide at a later stage. I'm more inclined with the first two.

How realistic ?, mmm, I'll know after the prototype is done. Anyway I'm planning to do small runs, 5 or 10 boards at a time.

An estimated price, just for the parts rounds 80 Euro or so (+- 30%). As we say in my country "at flying pig".

Btw. The software emulator will be under the GPL.

[hppacito]

For the proto I need to buy some components, make a PCB ;-). Roughtly a couple of months.

This will work as a replacement for the original processor. So
the emulator will run 68020 software, enough to be able to run OS 3.9 (processor-wise).

Native drivers for the IDE controller and ethernet, should bring better load times than the integrated IDE or external HD in the case of the A500, and better connectivity. A native stack may be can also be implemented.

The A600 has only some space constraints, but basically is very similar to the A500, and the same technique can be used to release the processor. The problem arises because the processor is PLCC and is soldered.

The flash will have the simulator, the kickstart will be copied to fast memory and run from there.

[hppacito]

@alexh:

If you can not do it, doesn't mean that no one else can not do it. Try to remember that before you post next time.
(With regard to KISS, I know the principle, pls: read about proto).

Rest:

Regarding the amount of many that costs, can be sell to. As is a hobbyst project, not a "I wanna make zillons of Euros with it nd save myself", I'll risk the money to make a proto and a final version. That's why the idea of small runs if somebody else is interested.

A500/A600 issue:

If from the start both processors are taken into account, that can be accoplished without that much trouble. But the limits of the board should be kept in mind.

A600 memory expansion:

That is not at all that difficult to make. (Wondering which DRAM chips are still available at low cost...). I'll see What can be done.

Emulationlayer: Everything depends on how fast you want it to run. If 1 MIPS is enough, can be done perfectly, if you want 100... let's look to something else.

Chipram: without a new Agnus... more than 1MB is a bit tricky. I'm not planning anything here.

Will be great to have a new A600. The custom chips, should be feasible in FPGA. I don't know if the amount of info available is enough to sytesize them. I wish I knew.

[hppacito]

@leirbag28:

I'd love if every comment is like yours !  :-)

The only 060 that doesn't cost an arm and a leg, is the EC060 @50MHz, only 88.79 for qty: 1000 !. Here, they run for a bit more :-(, and units.

Those cheap DVD players... Or they are stolen, or they get some kind of license. But volumes are what count regarding electronics.

Look, a 512kx8 SRAM chip costs 4.7 Euro per unit, if you go to 100, the cost just 3.20 Euro.

I'm auctioning for those EC020, hope I get 'em. I don't want to resell them, most stuff I think is bought by resellers, how is that they have 1000s of items purchased then ?, unglaublich  8-)

[hppacito]

@alexh:

great !

I am not saying I couldnt do it, or that you couldnt do it. I am an ASIC engineer, I've worked on multi-layer Set-top-box PCB's in the past. I have access to Protel, Orcad etc. I am sure that I could do it, but I have no real incentive to do it.

But I have the incentive to do it. ;-)

I have 10 years of experience with microprocessors, and already did quite a bit of things that more than one thought that were unachivable, anyway I know the risks, I know takes time, and I know takes money. I'm willing to, between some boundaries, put them.

Everything is expensive, but if nothing is done, we don't get anything. And companies don't seem too worried to release something.

The fast ram expansion is of course quite doable. I already considered it. But cheap, cheap, I don't think it is. may be 30 or 40 Euro. Anyway I wanted to do it from day 1, so it is in my pipeline (see my first post).

Let's see, may be you want to colaborate somehow.

[hppacito]

So guys (and girls ;-)), i got the 330 ec020, i'll put them in a a500 and a600 accelerator with 4MB SRAM (for the price, and speed gain, I think is worth over dram).

[hppacito]

Hallo Wayne !, are you listening ?

Could you please make a real poll with the options Doppe1200 wrote ?

The specifications will be:

A500/A600 Accelerator board:

Processor:    68EC020 @ 14.38 or 16.67 MHz
RAM:          4/6/8 MB Depending on A500/A600
PLCC socket:  empty, can be populated with a 68881/2
IDE Port:     1, buffered

I'm inclined to use SRAM, because requires far less logic, and can be faster (and can bring some overclock improvements). But DRAM would definetly lower the cost a bit .

So would be 2 Polls:

1st.

RAM Type:

Soldered SRAM (0 Wait state), populated
Socketed DRAM (1 Wait state), not provided

Price:

40 to 60 Euro
60 to 80 Euro
80 to 100 Euro
more than 100 Euro
All the money in the known universe
All the money in the unknown universe


Thanks !

[hppacito]

An FPU was suggested.

PLCC sockets are not more difficult to solder than other sockets (unless you use the smd version, I was not going to).
Expensive... a bit more, easy to broke, definitively !

As you know I got some cheap EC020. 030s are a bit more scarce and expensive (the run at 50 Euro in Spörle, for the 20MHz version). But a working design for a 020 can be made to work with a 030 in case of need, and some magical logic.

The only difference between the two is the socket (and the fact that you should remove the processor from the A500). Both sockets probably will not fit the same board at the same time. I'll see how cumbersome that is.

A600 accelerators are even more expensive on ebay :-(

[hppacito]

link to ec020 auction

[hppacito]

That's a sweet number !, let's see if he will offer some dram, Alice, Gayle o whatever the other ics are ;-).
I'll get mine next week... anyone else wants to get hold of them ? (If I buy more ics my gf will leave me :-(, there is plenty of nice electronic components... I just wonder _how_ they get them.... ) :-D

[hppacito]

But I'm not going to buy them. I won't finish an accelerator anyway because of earlier mentioned reasons.

Anyway, trying to make two acc for the same machines, in this case, is not the best option. Maybe try to do some other useful periperial, would be better.

[hppacito]

Actually, both use the same techniques.

The host processor in the A600 should be put to rest asserting BR. In the case of an A500... no processor to worry about.

Better to do a design for one, and the other one should be a modified PCB (I still think that with a bit more area, both can be done on the same PCB). That should not increase the price that much.

This is what I have in mind:

D0..D15 sould be buffered to isolate the high speed 020.
A1 to A23 should be isolated also through some '244.
Control lines should also be isolated
*UDS/*LDS should be generated. Remember that the 020 has dynamic bus sizing, so take care of SIZE0/SIZE1 and DSACK0/DSACK1.

The original Ax00 should only be accesed in the following mem areas:

0x000000..0x1fffff
0x600000..0x9fffff (A600)
0xbfd000..0xbfffff PIA (even addresses)
0xdf0000..0xffffff

*DTACK should be routed to *DSACK1 for 16 bit ports, but only in the mentioned regions.

In the Fast RAM region, should be internally generated (tyed to *AS for example, for a 3 cycle access to RAM).

I was also thinking in replacing the original Kickstart with a 32 bit version (read, with 4x8 bit epros or 2x16 bit eproms), for even faster access. That should need to get *ROMEN from the old ROM socket, or autogenerate it. But again *DSACK0/1 should be generated. If the new eproms are fast enough (could also be flash), that can be a 3 cycle access, or a 4 cycle access. A shift register can be used to generate the delayed signal.
Plenty of logic can be used to generate all this signals, may be a GAL can be cheaper, and cut on IC count, but I don't have a GAL programmer, though. I have to find a cheap GAL programmer, or make my own. I have an eprom programmer, though.

Regarding PCB costs, there is a shop in München, where they make small runs, 30 Euro (+16% VAT), each piece for 5 PCBs.
23 for 10. At 100x160 mm, 2 layers. That surface should be more than enough for this. This is the initial price, next runs are cheaper.

[hppacito]

@Doppie1200

The cost of running something _that_ professional would be prhibitve. I was planning in soldering myself ;-)
BTW, all components should be in reels, and so on and so on. Btw, the A500/600 are not lead free.

Somebody suggested some memory in 0xC00000, may be I forgot it in my memory map.
There are a couple of holes in he memory map that can be used for expansion. I'll see what can be done.

Somebody can/wants to burn some gals ?

[hppacito]

From what I see in the thread, he didn't get that far. People seem not to like the Apollo 030 that much. The increased memory size is quite sweet though. I'm pushing my proto anyways.

Somebody suggested a TRL8019AS or CS8900 as network controllers, anyone knows where those can be bought ?, seems that the CS chip is 10 bucks a pop, let's hope they are cheaper. (Read: reseller in germany willing to sell small qty), can also be an ebayer