Launched a DIY A501 Replacement Project

[kamiga]

Another one of my hare-brained schemes has been ill-conceived and is on its way.

Felt like learning more about how the DRAM sub-system works on the Amiga, so I've set off to create a new redesigned A501 512K memory module for the Amiga 500's.

I'm documenting all of the DRAM timing of the RAS/CAS's/Write Enable/68K latches because I don't think it's been done before. And I don't see it in any of the official documentation.

So I'm starting to put up Logic Analyzer traces that have all the important details.

I'm using about USD $2.50 worth of glue logic parts, and < $5 memory SRAM chip.(SRAM?!@# the horror). The 56-pin header connector is one of the expensive parts, around $4.

The glue logic to convert DRAM RAS/CAS -> Chip Enable works in simulation, testing in hardware is forthcoming....

Project detailed at

http://www.techtravels.org/amiga/amigablog/?page_id=942

with blog posts at

http://www.techtravels.org/amiga/amigablog/?cat=28

Everything is open-source/open-hardware.

Constructive comments always appreciated.

Thanks
kamiga

[kamiga]

Awesome!  I actually had a pretty tough time finding an A501-clone that didn't have battery damage, so hooray for new Amiga hardware!  Also you could probably make the 1MB ones that go to the A500+ with little modification to your design, those seem relatively rare (and expensive), also!

Yeah, in general I'm happy to see more new hardware in the amiga scene. Every extra breathe of life we can blow into the amigas is good.  This is a learning project for me,  but helps sustain the existing machines I have....

Yes,  extending this project to support 1mb should be easy enough.  Where do they get the extra address bit?

@magnetic: more about the journey than the destination my friend.

Thanks
Kamiga

[kamiga]

This could actually be quite interesting for internal expansion. You could implement something like the kcs PowerPC, or ide or whatever.

Yup, and this thought definitely hasn't escaped me.

You could imagine that you could create any number of memory-mapped I/O devices.  Wikipedia says the Commodore 64 could bank switch between memory and the devices. [1]

I think useful throughput through the memory interface is somewhere around the color burst freq of 3.57mhz or so.  That's not horrible, and I have a couple decent ideas of how this could be used.

Thanks
kamiga

[1] http://en.wikipedia.org/wiki/Memory-mapped_I/O

[kamiga]

I thought I'd mention that I just commissioned the creation of the PCB for this project.

http://www.techtravels.org/amiga/amigablog/?page_id=942

About (2) months (of nights and weekends here or there) from concept to PCB including building a mostly working solderless breadboard version.  Not too bad.  Not let's see if the darn thing works when it gets here.

Thanks

[kamiga]

Thought I'd mention that the finished PCB is fully working, although I'm continuing to do some testing on it.

I've added some photos:

http://www.techtravels.org/amiga/amigablog/?page_id=942#Photos

[kamiga]

Within a few days.  It's not very complicated.

The RTC portion is pretty textbook.  It worked the first time on the PCB with no prototyping done at all.  Just hooked it up, and it works!

The RAS/CAS/CE glue logic is only a few gates and a SR latch.

I'll try to put it up this weekend.

[kamiga]

As promised, schematics are now available.

I've got more stuff to put online, but just have to find the time.

I'd suggest downloading the PDF.  The plot-to-clipboard function of KiCad yields some fairly low-res images.

http://www.techtravels.org/amiga/amigablog/?page_id=942#Schematic