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Next we consider the Buster chip. The Buster in the A3000, Rev 6 or Rev 7, is a well proven design. The difference between the two is only that there was a small bug in Rev 6 that caused it to fail at 16MHz, but it works fine at 25MHz. These are what we called Level I Busters; they don't support Zorro-3 DMA or Quick Interrupts, and they don't attempt to translate local bus burst cycles into Zorro-3 burst cycles. Starting with the unreleased Rev 8 Buster, we went to Level II, which is roughly twice the size of the Level I design. Level II Buster supports Zorro-3 bus arbitration, DMA, Quick Interrupts, and translation of local bus burst cycles into Zorro-3 "Multiple Transfer" cycles. There are two of these parts released: Rev 9 and Rev 11. The Rev 9 Buster has a few flaws. The primary flaw, and the main reason the part was revised, is that the Zorro-3 bus arbiter can jam under the right conditions. Some DMA cards, like FastLane Z3, use a workaround for this (they avoid the lockup condition), others don't, and will lock up when used with a Rev 9 Buster. There is also a potential problem with end-of-cycle synchronization in the Rev 9 part. Some Zorro-3 cards will demonstrate this problem, some won't. This is made worse by the STERM* sampling problem on the Rev 3.0 A3640. A final problem with Rev 9 Buster was introduced by the A4000 architecture. The integrated bus buffer, Bridgette, used in the A4000 can't quite guarantee the propagation times required by the Rev 9 Buster design (done before Bridgette was proposed). In the typical case it works fine, in the worst case some Zorro-3 cards will have a problem with this condition
Darrin wrote:Ah, thanks for that tip. I picked my A3000 up second hand so I'm not sure what the Buster revison is. What happens if it is an older one?