Improve the old 7MHz bus/chipset speed. 12.5MHz would be nice and would work with the same 80ns DRAM. There wouldn't be time for two memory reads within two clocks, behind the CPU's back, as there is on AGA, but a longer burst read could be used and bandwidth would be almost the same without it anyway. Other benefits: blitter runs faster, 12.5MHz/25MHz gives a proper 320/640 wide resolution on a VGA monitor.
Scanline buffering: so the bus speed doesn't need to divide evenly into the pixel clock, and enabling scan doubling with full backwards compatibility
Chunky 8-bit mode. Possibly with a mixed-mode where if the high bit is set then the low 7 bits are combined with the next byte to make a low-res 15-bit RGB pixel. So 128-color high-res could be mixed with 32K-color low-res.
2-4 more sound channels with high sampling rates (video scanrate independent) and the possibility to combine two 8-bit channels into one with 16-bit resolution.
Other Paula improvements to enable high serial port speeds without dropping bits and high density floppies at the normal rotational speed.
Make it so the blitter can handle 32-bit word size
